Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
mb-gdb: problem simulating memory mapped i/o devices
Hello, I'm trying to simulate a C program in MB-GDB but I get trouble when trying to simulate memory based I/O devices. I'm not using Microblaze but a improved Openfire core (same ISA) so microblaze...
 
xps error never seen before: google reveals nothing; help!
(reposting with catchier subject line and some changes...) Hi, We are trying to run the "Virtex4_PPC_Example_9_1" example program from EDK9.1.2 that has TestInterrupt.c routine (timer interrupt...
4
4
 
Xilinx XC4VLX40-10FFG1148C - Available New
I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference: ?name=122-1491-ND Please let me know whether anyone will by...
 
SDR SDRAM controller for Xilinx Spartan-3E
Hello, I would like to utilize a controller for a SINGLE data rate SDRAM (Micron MT48LC16M16A2TG-75, to be specific). In the past I've used Xilinx' MiG 1.4 to obtain a DDR2 controller, which I ended...
15
15
 
World's 1st FPGA Centric Portal goes LIVE!!
FPGA Central is the central place to find complete information about FPGA Vendors, FPGA Products, IPs, FPGA Events, FPGA News and so much more. Field Programmable Gate Array aka FPGAs is a...
 
camera module interface to FPGA
hi I am trying to interface a camera module to FPGA board. i am new to VLSI. can any suggest and help me out of where to start and how to proceed. i am working on Altera DE1 board. not sure yet of...
1
1
 
Spartan 3E starter kit DDR SDRAM
I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread. Is there such a demo out, mentioned in the thread? I read in several groups that it is a problem to get this DDR Ram...
5
5
 
V4FX PPC suspend/resume
We want to be able to save our PPC state to ram, shut off our fpga, and be able to restore the PPC when we wake up later. Seems like this should be a pretty common problem. Can anyone suggest how best...
5
5
 
Download the contents of the FPGA's RAM block
I have FPGA DSP design that has several RAM blocks. What is the easiest way to transfer the content of the RAM to the PC? I am using Xilinx Virtex-4 ML402 board with Platform Cable USB. Thanks, Dan
6
6
 
Forwarding engines
Evnin' Does someone knows of any books or other reading material which covers the design and implementation of forwarding engines and IP route table lookups in FPGA/ASIC? thanx in advance rick
 
Altera-Xilinx interfacing SERDES transcievers problem
Hi, Who could enlighten me with the followings: I need to interface a SERDES transciever from a VIRTEX5 FPGA with a STRATIX II IO. Things would be easiest if I'll have a Stratix II GX instead of...
3
3
 
V4 DSOCM always reads back zeroes
Hello, I have a ML403 PPC design (XPS 9.1) that executes code out of DDR. I added 16 KByte of on chip data side BRAM, but the new memory space only seems to read zeroes and ignore writes. I think I...
1
1
 
Inputs as an Array in Verilog??
Hi Guys: I am working on an application where I have a large number (264) inputs to a single Verilog module. Each input is an 8-bit number. I would like to be able to refer to these inputs as members...
1
1
 
Position at The MathWorks
The MathWorks has an open position for an HDL Applications Engineer. If you are interested in this position and would like to find out more, please send your resume to AT
 
DOSFS for EDK
In an earlier thread complaining about the state of the Xilinx website, Antti (by mistake?) signed off with a URL thus: Antti micro-SD adapter for digilent/xilinx boards: At this URL there was a...
2
2