Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
AREA_GROUP Map Error
I have a design that instantiates four copies of a module and I am using Xilinx's AREA_GROUP constraint to partition each instantiation into its own 1/8th sector of the FPGA. I ran across a few...
1
1
 
Problem about clock switch in Quartus II 6.0
I use Cyclone II to implement image processing. There are a CMOS image sensor, a FPGA chip, and a SRAM on my board. I meet a new problem when I try to optimize my design. In my old instance, I use the...
4
4
 
Exciting openings for Standard Cell libraries/Memory designer in a fortune 50 organisation
Hi All, This is Nitin Gupta from Itprogress. We are a Noida based executive search firm specializing in targetted search of professionals. We are looking for Sr.Engineers/Managers- Standard Cell...
 
Need suggestion for my project
I am now preparing the project: encryption data stored in the SATA disk. I want to realize a device placed between the pc and SATA disk as following: PC SATA controller FPGA board SATA disk I planed...
7
7
 
xilinx plb_ddr to self refresh mode
Can anyone tell me how to command the plb_ddr core to put my external ddr sdram into self refresh mode? Thanks, Clark
2
2
 
new to the group
hi all, i am new to this group and i am beginner in this FPGA field so i need ur help to find some material regarding FPGA i hope u people can help me out thank u
4
4
 
DSP design into FPGA
hi all.. Is it possible to import the design which is converted into a file by Altera DSP builder into SOPC builder. i have converted it into a *.ptf file but was unable to import into the design. can...
 
how to test the FPGA on the board
hi all I have to test an fpga on a customised board could anybody suggest me the methods for this archana
1
1
 
Single Ended signal in sync with V5 GTP
I need to generate a signle ended signal possibly using the V5 Select I/O pin that is synchronous to one of the GTP output running at 400Mbps. The sigle ended signal needs to be 1.5V Push-pull type. I...
5
5
 
bidirectional pin
Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that in VHDL there is keyword "inout" when defining port, but I don't know what...
8
8
 
FPGA accelerator service
Hi. I'm looking for a company who implement various algorithms using FPGA accelerators. Who can take part of some software code and rework it completely to make working FPGA accelerator in form,...
1
1
 
OpenSPARC
Hi. Does somebody have a real success with burning OpenSPARC to FPGA?
3
3
 
bare bone PCI cards with FPGAs
I have a certain demand on processing digital data with a PC and thought about to do this with an FPGA/PC. What would be fine was a PCI compatible card with an FPGA on it which could be extended to my...
1
1
 
Confused about my behavioral simulation under ISE 9.1
Gang I created a module, downloaded it to my dev board and ran it. The LED's changed as I expected. I decided to run a behavioral simulation to prove to myself that signals were changing the way I...
2
2
 
Area report
I am reading some papers about algorthms implementation. I noticed they like to compare the synthesis area of the fixed-point implementation. I wander where they find the area report for the...
3
3