Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Master Xilinx FPGA like Jtag bridge.
How to make master FPGA to connect to many FPGAs ? Two FPGAs connected by serial TDI - TDO, and two fpgas TMS TCK TDO and TD I connect to master fpga, master fpga has TMS TDI TDO TCK connected and wor...
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7 years ago
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designing a fpga
Hi all, A couple of weeks ago, I was watching the talk of Wolf Clifford on his opensource fpga flow at ccc. () At the end, he mentions designing an open-source fpga and the replies he got when he...
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7 years ago
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CFP: The International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE)
The International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE) ISSN : 2394 - 0816 Call for papers *************** The International Journal of Applied Control,...
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7 years ago
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cmos delay vs temperature
I found one old Fairchild appnote that has some numbers which averages to around +3000 ppm/degC, or about +3 ps per ns of prop delay per degree C. That's with 50 pF loading, sorta high. This is HC,...
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7 years ago
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Intel (Altera) announces Cyclone-10
It looks like Intel has learned to count from Microsoft. The previous generation of Cyclone was Cyclone-5.
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7 years ago
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All-real FFT for FPGA
So, there are algorithms out there to perform an FFT on real data, that save (I think) roughly 2x the calculations of FFTs for complex data. I did a quick search, but didn't find any that are made...
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7 years ago
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Go to church
That still small voice you hear on the inside, the one drawing you from within, reminding you of the things you should be doing, and pointing out the things you shouldn't be doing ... listen to it....
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7 years ago
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Hardware floating point?
So, just doing a brief search, it looks like Altera is touting a floating point slice in at least one of their lines. Is this really a thing, or are they wrapping some more familiar fixed- point...
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7 years ago
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Anyone use 1's compliment or signed magnitude?
This is kind of a survey; I need some perspective (possibly historical) Are there any digital systems that you know of that use 1's compliment or signed-magnitude number representation for technical...
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7 years ago
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VHDL Editors (esp. V3S)
As X and A's integrated editors are more or less limited, I guess many peop le will looking for better alternatives. The usual suspects will be Emacs (with VHDL mode) and Sigasi. For me personally, I...
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7 years ago
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VHDL, how to convert sensor data to Q15
Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers, who can help how to convert it to Q15 data format in...
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7 years ago
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Terminating an Aurora link in a PC
Hi I have two devices communicating via an Aurora link (single lane, full duplex) over SFP + optical cables. I need to replace one of them with a PC (testing, emulation etc etc) I see several (HITEC...
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7 years ago
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I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
Hi, I am doing a small exercise to learn verilog on FPGAs trying to create a FSK31 (ham-radio digital mode) from a FPGA using DDS. The boards I have use either a Spartan6 (XC6SLX9) or an Cyclon IV...
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7 years ago
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VHDL I2c burst read
Dear All, please help with VHDL, i connected MPU6050 to my FPGA board. I used tutorial, can anybody exlpain me how to read burst data 16 bits from 2 registers or 6 regsiters ? by only one operation ?...
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7 years ago
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Happy New Year! Go to church Sunday (first service of 2017)
Go to learn about how to be forgiven for your sin, and to pass from death (because of sin) to life (eternal life, spiritual life). Christianity is not a religion. It's a relationship with Jesus...
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7 years ago
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