Field-Programmable Gate Arrays - Page 87

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• 03-17-2007
• XPower crashes....
• • Xesium
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• 03-17-2007
• Use of both positive reference and negative reference of the same signal for Xilinx chips ...
• • Weng Tianxiang
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• 03-17-2007
• Xilinx XST 9.1, Verilog 2-D arrays, always @*
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• 03-17-2007
• Systemverilog preprocessor allow "..."?
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• 03-17-2007
• What official function should I call to genertate a sum of products in VHDL
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• 03-16-2007
• Xilinx ISE support for dual/quad core CPUs?
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• 03-16-2007
• Virtex5 LXT and synthesis..
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• 03-16-2007
• Xilinx Synthesis Attribute usage
• • Joel
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• 03-16-2007
• XILINX ISE: How to define a Internal clock and use it in OFFSET command?
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• 03-16-2007
• chipscope
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• 03-16-2007
• init of FPGA's Block-RAMs.
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• 03-16-2007
• How to generate sgmii interface?
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• 03-16-2007
• old Quartus project files
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• 1

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• 03-16-2007
• Problem with XESS XSA 3S1000!
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• 0

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• 03-16-2007
• How to use the DDR SDRAM instead of Block RAM?
• • Ken Soon
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• 10

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• 03-16-2007
• DCM Autoconfiguration??
• • motty
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• 4

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• 03-15-2007
• XIlinx 9.2 'partition' mode problem - s/w dies....
• • johnp
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• 1

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• 03-15-2007
• ChipScope problem: "Waiting for core to be armed".
• • Rebecca
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• 7

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• 03-15-2007
• Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Trans...
• • Jhoberg
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• 0

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• 03-15-2007
• Fpga sdr boards / kits
• • Alex Gibson
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• 0

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• 03-15-2007
• Xilinx Xplorer misfunction
• • Frai
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• 03-15-2007
• doubt in verilog coding
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• 03-15-2007
• DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY
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• 03-15-2007
• .bit file to VHDL/verilog source code
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• 1

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• 03-15-2007
• Welcome to X-Fest 2007
• • Peter Alfke
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• 0

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• 03-14-2007
• SEC:U Problem getting rid of bit latch errors
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• 3

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• 03-14-2007
• Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30)
• • Pablo
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• 03-14-2007
• Clearing fpga internal memory...
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• 03-14-2007
• Xilinx Netlist
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• 03-14-2007
• Xilinx FPGA, OFFSET OUT AFTER
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• 03-14-2007
• interface ad9229 with altera stratix II
• • michael
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• 03-14-2007
• Programming XCF from MicroBlaze over JTAG???   [ 2 ]
• • Bob Golenda
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• 25

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• 03-13-2007
• ANNC: Clock Network Implementation Webcast
• • bart
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• 0

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• 03-13-2007
• qemu+ghdl or uml+ghdl hardware-software cosimulation?
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• 1

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• 03-13-2007
• PCI - Express
• • Tim
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• 1

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• 03-13-2007
• using system ACE for generic app data storage - file system intelligence required?
• • Jeff Cunningham
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• 1

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• 03-13-2007
• WTF? - Spartan-3E starter kit with no printed board manual?
• • Uncle Noah
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• 8

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• 03-13-2007
• Xilinx SRL's and sync flip flops
• • motty
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• 03-13-2007
• sum of array
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• 03-13-2007
• Modelsim - SDF incompatibility
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• 03-13-2007
• Can you change the default settings for XST when running platgen?
• • Rick North
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• 03-13-2007
• help !something wrong with Adaptive Filter (vhdl code)
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• 03-13-2007
• faq
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• 03-12-2007
• 3.3V tolerant Virtex-4 JTAG Configuration
• • Dale
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• 03-12-2007
• Heatsink on FPGA?
• • jean-baptiste.nouvel
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• 9

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• 03-12-2007
• /* synopsys enum state_code */ on XST???
• • jean-baptiste.nouvel
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• 1

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• 03-12-2007
• PAL
• • Peter Soegaard
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• 1

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• 03-12-2007
• Initialization of arrays in Verilog
• • Till Wollenberg
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• 3

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• 03-12-2007
• ISE synthesis works, XPS does not resolve symbol?
• • Bhanu Chandra
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• 1

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• 03-12-2007
• Estimating number of FPGAs needed for an application
• • rbblasco
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• 6