Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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mixed Verilog/VHDL in ispLever 7.0 broken
G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core module wrapped in a Verilog top file would fail with Precision...
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16 years ago
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SATA OOB using Rocket IO (Virtex 5)
Hi All, Does anyone have information on using Rocket IO of Virtex 5 for SATA OOB. I would be grateful if anyone can send me a link to the document that details the connection settings. Thanks,...
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16 years ago
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edk + spi
hi is there a reason why the clock divisor for the spi clock in edk 9.1 cant be smaller than 16? i would need 4. is there a way to do that or do i have to write my own spi module? thanks urban
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16 years ago
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new xilinx forums
are open if someone didnt notice yet Antti
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16 years ago
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Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
I have a design where I use a 40MHz input clock to create a 40MHz, 80MHz, and two variable-frequency output clocks. The variable- frequencies are 80/120, 40/60, 20/30, 10/15, 5/7.5, and 2.5/3.75...
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16 years ago
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Using Virtex-II Pro MGT with external CDR
Hi, I would like to know if anyone has experience with connecting an external CDR or CPA to a Virtex RocketIO MGT. I am using the Virtex-II Pro MGTs in an optical CDMA application where the receiver...
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16 years ago
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Design Behavior affected by use of Chipscope
Hello everyone, I have encountered a rather strange behavior in one of my FPGA Designs. i have a DDR2 RAM controller (generated partly with the Memory Interface Generator) in a Xilinx Virtex-4 FX60....
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16 years ago
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Problems using xilfatfs on XUP V2Pro board
Hi there, I've been using the Xilinx University Program Virtex-II Pro development board and I'm having great trouble writing code to interface to the SystemACE compactflash system. I expect my program...
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16 years ago
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Xilinx 13th August opportunity
quote from Xilinx webpage: "Xilinx is upgrading its forum software. These forums, along all their content, will be retired on August 30th, 2007. Starting August 13th, you will be given an opportunity...
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16 years ago
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edk+uclinux ??? <about make dep>
what's wrong with following word??? [root@localhost uClinux-dist]# make dep make ARCH=microblaze CROSS_COMPILE=mb- -C linux-2.4.x dep make[1]: Entering directory...
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16 years ago
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regarding the clock issues in the fpga...
hi all, i have got one problem: i have designed sonet sts-3c framer/deframer where it works at 155mhz freq which i am getting it form the optics card whrere CDR(clock data recovery circuit outside the...
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16 years ago
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LUT distributed memory in FPGA devices
I wanted to add to the thread at does SRL exist in non-xilinx FPGAs? But i got the message: replies are not allowed ? i really don't why? and who adds this constraint. as such i am opening this thread...
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16 years ago
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Used Stratix II FPGA's
Hi, Where can one get used Stratix II FPGA's. Thanks, Eswar Saladi email :
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16 years ago
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ucf editor edk
hi i have a question. do i have to edit the ucf file by hand in edk 9.1 or is there a editor like in ise? i thought i could use the editor from ise but my ucf file that i created with edk wont load.....
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16 years ago
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How to locate the internal state machine in timing simulation
I am using VCS compiler to do the Xilinx FPGA timing simulation. I have 16 bit state machine in one of my verilog submodule. I am able to do the timing simulation but not sure the exact proecdure in...
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16 years ago
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