Field-Programmable Gate Arrays - Page 90

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• 02-26-2007
• OFFSET and Data Clock Skew?
• • Brandon Jasionowski
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• 1

• 
• 02-26-2007
• Spartan-3AN   [ 2 ]
• • Antti
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• 40

• 
• 02-26-2007
• ML501 Platform Flash Configuration
• • self
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• 2

• 
• 02-26-2007
• Virtex 4, how do I generate 100khz clock
• • jim
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• 3

• 
• 02-26-2007
• Xilinx platform cable USB API?
• • MotM
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• 7

• 
• 02-26-2007
• XC3S400 and XC3S500E in PQ208
• • Uwe Bonnes
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• 13

• 
• 02-26-2007
• Xilinx ISE webpack in Ubuntu?
• • Steve Battazzo
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• 16

• 
• 02-26-2007
• Edge vs Level triggering
• • mahenreddy
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• 1

• -
• 02-26-2007
• OPB BRAM not detected in EDK
• • Venu
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• 0

• -
• 02-25-2007
• Bluetooth standard in software defined radio
• • Mohamed Bakr
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• 0

• 
• 02-25-2007
• Making a 32KB BRAM block, virtex-4
• • Bhanu Chandra
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• 15

• 
• 02-25-2007
• Xilinx Platform cable USB and impact on linux without windrvr   [ 2 ]
• • Michael Gernoth
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• 22

• -
• 02-24-2007
• MIG 1.6 on ISE9.1i
• • El-Mehdi Taileb
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• 0

• 
• 02-24-2007
• How to specify ISE INST constraint with GENERATE statements?
• • Brandon Jasionowski
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• 3

• 
• 02-24-2007
• Interfacing to 10Gig ethernet with Xilinx FPGAs
• • Marc Kelly
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• 7

• 
• 02-23-2007
• Small FPGA Dev Board with Ethernet
• • Chris Murphy
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• 2

• 
• 02-23-2007
• SystemVerilog?
• • Andreas Ehliar
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• 4

• 
• 02-23-2007
• Help for video compression
• • VHDL_HELP
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• 1

• 
• 02-23-2007
• demande aide
• • abaidik
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• 7

• 
• 02-23-2007
• Not power of two BRAM size problem
• • Andrea05
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• 3

• -
• 02-23-2007
• Chipscope with Spartan 3E Starter Kit
• • Dominik Domanski
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• 0

• -
• 02-23-2007
• Need help to buy first FPGA board!
• • dang_hut
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• 0

• -
• 02-23-2007
• Need heep to buy first FPGA board!
• • dang_hut
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• 0

• 
• 02-22-2007
• Structured ASIC players
• • John_H
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• 3

• 
• 02-22-2007
• internal DCM
• • mahdi
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• 5

• 
• 02-22-2007
• 2x technique
• • mahdi
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• 3

• 
• 02-22-2007
• MicroBlaze and OPB block ram interface controller run at different frequency
• • David
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• 1

• 
• 02-22-2007
• porting virtex2-pro into virtex4. Performance!!
• • lkjrsy
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• 4

• 
• 02-22-2007
• VHDL code for Generating registers
• • Sandip
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• 2

• 
• 02-22-2007
• Using Xilinx DCM FX output without DLL
• • dipumisc
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• 2

• 
• 02-21-2007
• Determine error in asynchronous signal
• • axr0284
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• 14

• 
• 02-21-2007
• Can someone give me some pointers on using ibis models?
• • Teece
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• 3

• 
• 02-21-2007
• OPB IPIF: write to DIER causing bus timeout
• • Neil Steiner
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• 1

• 
• 02-21-2007
• how to use STD_LOGIC_VECTOR2
• • Pasacco
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• 1

• 
• 02-21-2007
• up down lfsr
• • jams
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• 2

• 
• 02-21-2007
• nets vs. pads ; constraints question
• • vu_5421
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• 1

• 
• 02-21-2007
• Cyclone II "altsyncram" timing constraints?
• • Jules
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• 3

• -
• 02-21-2007
• Extended CFP for CIC 2007: (submission date extended to March 9, 2007)
• • dauriol
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• 0

• 
• 02-21-2007
• newbie question
• • vlsi_learner
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• 1

• 
• 02-21-2007
• RTOS?
• • Surya
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• 1

• -
• 02-20-2007
• Spartan-3E Sample Packs
• • ziggy
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• 0

• -
• 02-20-2007
• Looking for a superscalar simulator
• • Patrick
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• 0

• -
• 02-20-2007
• PETALINUX AUTO-BOOT
• • Pablo
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• 0

• 
• 02-20-2007
• Selecting device in Project Properties : no XC2V1000?
• • Vladimir Orlic
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• 4

• 
• 02-20-2007
• can I convert DPRAM to SPRAM?
• • vlsi_learner
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• 5

• 
• 02-20-2007
• Xilinx ML402 Virtex-4 Eval kit - I2C Bus
• • m.afgani
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• 1

• 
• 02-20-2007
• Managing input clock of 20MHz at input of DCM
• • mh
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• 2

• 
• 02-20-2007
• configuring in slave serial mode with serial platform PROM
• • ekavirsrikanth
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• 1

• 
• 02-20-2007
• How to get the area/time results without IO mapping
• • Aaron
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• 4

• 
• 02-20-2007
• Xilinx MIG DDR2 Documentation
• • Erik Widding
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• 3