Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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MCS -> BIT
Hello I have just the MCS file and I want to configure directly my FPGa with a bitstream. So I had to convert the MCS in BIT. What I have done: 1)MCS->HEX with promgen: promgen -r -p hex 2)HEX->BIT...
4
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16 years ago
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4 | |
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Globally Asynchronous in FPGA
Hello Let me ask one question. design, because (1) There are enough registers, (2) There are fat clock trees for entire chip, (3) There are IPs for different clock synchronization management (for...
6
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16 years ago
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6 | |
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Xilinx / ISE multi-cycle path constraint pitfall
Hello, To summarize the issue briefly: I have a group of flip-flops which toggle every 4 clocks by using an "clock enable" signal, but I can't define a multipath constraint according to this signal....
26
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16 years ago
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26 | |
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DDR controller - best device to perform
Hello I decided to make my own DDR controller. I want to do this on CycloneII or Spartan-3 I'm not decided yet. That's way I want to ask the quastion: Which of this device familly has better features...
16
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16 years ago
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help on camera ports
i have a posted for a camera and i was suggesed the following. it is 1/3 Color Camera Mod C3188A-6018 Digital output.i am attaching its datasheet.( have a problem in knowing what its ports are from...
1
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16 years ago
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1 | |
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Xilinx Constraints Question
Hello group, We are modelling our ASIC in an FPGA (Spartan) for system testing and as a demonstrator. For power reasons, we have globally (centrally) gated clocks of frequency f, f/2, f/4 etc (named...
4
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16 years ago
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4 | |
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Minimal power?
Hello, How feasible is it to shut down (or place in low power mode) an fpga (eg. XC3S1000 from Xilinx or similar) and power it up when it is needed (eg. after some interrupt to a microcontroller) ? If...
4
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16 years ago
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4 | |
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Actel APA1000 and JTAG
Hi all, We are trying to programme a FLASH memory linked to a APA1000. However, we have a data-blaster that should programme the FLASH quickly, providing we can drive the write signal from teh APA to...
2
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16 years ago
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2 | |
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Slice equation in bitstream
hey, in FPGA-Editor i can choose a slice and type in an equation for this block. i need information, where i can find this equation (truth table) in the generated bitstream and how they are arranged....
14
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16 years ago
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14 | |
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iMPACT command for selecting remote host running CableServer?
In the Xilinx EDK tool flow it is possible to synthesize a design and automatically program it into your FPGA using iMPACT. Therefore, a standard iMPACT command file is generated, which typically...
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16 years ago
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FIFO16 on virtex4 error?
I am currently using FIFO16 with xilinx Virtex-4. I found out in my design, the "almostempty" "almostfull" "empty" "full" flags are all stay high. That means some errors happen. The FIFO16s are...
4
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16 years ago
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Reconfiguring a Virtex4 DCM_ADV.
Hi All, From reading UG071, part of the Virtex4 user guide, I see that I can reconfigure the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes on-the-fly using the DCM's dynamic reconfiguration port. Very...
3
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16 years ago
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3 | |
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Routing JTAG pins thru FPGA
Hi, This is my first post to this group. I am an FPGA newbie trying to learn this new and exciting stuff. I have a set of 3 boards from an amateur radio project. Board #1 is a back plane where board...
3
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16 years ago
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3 | |
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FPGA :'define not allowed in ISE ?
Hi I was using 'define in my verilog file, while trying to compile the code using Xilinx ISE 7.1 I was getting error ? Could anyone please help me in this regard Rgds bijoy
1
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16 years ago
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1 | |
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Scilab / Matrix
Hi all, I need to implement a SCILAB matrix code into a FPGA (vhdl or verilog code , use dsp block, or any others solutions). => Any help is highly appreciated (exemple, user guide, etc...) !. => Do...
1
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16 years ago
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