Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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OCM BRAM and PCC issues...
Hello All, I am using Virtex II pro for a design with PPC,Timer, Bram, OCM, PLB,OPB. The Bram is attached on the OCM bus. I have done the Bram's PORT_B ports as external in order to load a stimuli...
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16 years ago
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DDR2 controller V4 vs V5 differences ?
Hi, I've been working on Virtex 4 with a DDR2 controller for about 1 year now and it works fine. The controller is based on MiG generated controller that we modified. The changes were some little bug...
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16 years ago
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Speed test between FPGA and DSP or PC.
Hi, I would like to make a test in which I try to prove the differences in speed between DSPs and FPGAs. The test could be implemented in C for the DSP or the PC, and in VHDL for FPGA. Perhaps some...
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16 years ago
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Inout ports in EDK
Hello everybody, I am having trouble incorporating a inout port of my custom peripheral in EDK. I found that the wrapper of the custom IP expanded a inout port into a tri-state _I/_O/_T. I read past...
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16 years ago
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Annoying
Hi all, Am I the only one who finds the digital magazine subscription of Xcell Journal very annoying? Is there a place where I can download the new editions as a pdf-file? Thanks and Regards,...
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16 years ago
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ROUTING=CLOSED in Xilinx 9.1 PR tools
I want to build a reconfigurable region that has no static routing inside. In the 8.2 version of the tools this was possible using the ROUTING=CLOSED constraint of the AREA_GROUP for the...
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16 years ago
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Altera DDR Controller, Modelsim and Verilog
Hi Forumees, Anyone have any experience simulating the verilog model of the DDR SDRAM Controller in modelsim? I am trying to use the following command - #compile the encrypted ddr controller in the...
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16 years ago
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ML365
Hi Does anyone know where I can get a copy of the gerber files for the ML36 board? cheers Jon
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16 years ago
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xilinx usb cable question
Hi, Does anybody have any luck with running the Xilinx usb-cable driver on a Linux 64 system? I'm having severe problems with this. I have done the steps below but have run out of ideas. 1. system is...
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16 years ago
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comparison with embedded processor
Hi all, I need to implement this code (below) with a embedded processor FPGA. Do you have any information to help me in the choice of this FPGA (performance) Altera // niosII, Xilinx // microblaze...
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16 years ago
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how to bidirectional signal in xilinx EDK tool ?
hi all i am facing a problem with EDK tool. can you please assist me in this problem is :- i am using a top file of name opb.vhd, which using a INOUT signal.when i synthesis using EDK tool , a...
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16 years ago
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Burst Memory Transfer Request from PPC
hi all, I'm working on the ML310 board, using EDK8.2i. I'd like to know how can we write c codes that executes burst data transfer on the PLB. Can this be done directly on the PPC core or do we have...
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16 years ago
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Power Reduction Strategy
I have a design on a Spartan 3 2000. It uses nearly all slices, two thirds of the FF and LUTs. Also all BlockRam and all BlockMultiplier are used. The design uses three clock. A 40 Mhz clock for...
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16 years ago
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Need to force all signals in a design to a known value at start of simulation
Hi, I have a VHDL design which has no reset, within the design are statements that rely on the last know state of a signal i.e sig_a
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16 years ago
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ML401 (Virtex 4 development board) as a USB peripheral
I'm trying to get the Cypress Ez-host working in peripheral mode on a Xilinx ML401 development board. The example code I have is for the actual cypress development board, but I don't see why anything...
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16 years ago
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