Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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An FPGA startup is seeking testcase from potential customers
Hello, Silicon Blue Technologies is an FPGA startup located in Sunnyvale CA. The FPGA product it is developing has ultra low power consumption and is targeted to low power applications. The company is...
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16 years ago
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Die size, pitch size?
Dear When I look at Virtex-II Pro data sheet (DS083 v. 4.5), page 7, I see following table. ------------------------- Package FF896 Pitch (mm) 1.00 Size (mm) 31 x 31 ------------------------- I guess...
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16 years ago
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Reconfiguration of a XUP Board
I am using a XUP development board for my project. It is this one: I want to reconfigure this board from a second board (same one). The configuration stream is stored in the DDR RAM of the second...
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16 years ago
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PCB Impedance Control
Hi If I am designing a pcb using impedance controlled layers can I treat th power planes as a reference layer as well as the gnd layers? Cheers Jon
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16 years ago
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Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
Hello! I would like to change the FPGA in this board to a bigger one, but I don't know if it's possible. I noticed in the datasheet ( that the 500 and 1200 versions are pin compatible (FG320), so my...
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16 years ago
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modelsim
Hai all, Can any one suggest with an example how to run c++ code in modelsim simulator...I didnt understand the example mentioned in modelsim user guide..Anyone tried this?? regards, fazal
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16 years ago
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Spartan3E and DDR termination
Hi all, We are building a board with Spartan3E (XC3S1200E FG320) and a 64MB x16 DDR (HYB25DC512160CF-6). Trying to make the board as tiny as possible the DDR termination presents a problem. Since the...
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16 years ago
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Xilinx FPGA Based Board Problem
Hi All, I am new to FPGAs and my main interest is implementation of some signal processing algorithms on FPGAs. For testing the MEMEC (DS-BD- V2MB1000) board which has a xc2vc1000 fpga on it along...
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16 years ago
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Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
Hi, I realize that in cfg.vhd files generated by PCI32 LogiCore does not have command register and status register. From Mindshare book, it said it is "always mandatory" to supply this information....
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16 years ago
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SDF File basics
What does SDF, and Back-annotation/Forward annotation mean? How is an SDF File generated and by which tool? Can someone explain how to do synthesis and what tools/file extensions (.sdf, .lib etc)...
2
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16 years ago
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Output signals not synchronized
I have 23bit wide RAM that I use as ROM inferred from the code. When I use the logic analyser (Agilent 16903A) with the finest resolution of 2.5ns I see that signals on the output header are not read...
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16 years ago
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Difference in the JTAG instructions between Virtex and Virtex II
Hi, I am writing a C/C++ driver for programming a Virtex 2 using the JTAG port (Parallel III cable) since it's required for a particular application (JBits) I found the required boundary scan...
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16 years ago
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Registered output for Altera on-chip memory
When generating a memory block for an Altera Stratix chip using the Megafunction generator, the tool defaults to registering the 'q' output port. I am curious, is there a particular reasoning behind...
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16 years ago
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PCIe question
The lane signals should be AC coupled: a. on the motherboard between the controller and PCIe socket b. on the PCIe card between the FPGA GTP and PCIe PCB connector c. on both ? thx, Vasile
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16 years ago
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OSERDES behavior
Hello, I'm trying to understand exactly what the behavior of the OSERDES is ... I'm using a 4:1 DDR mode for both data and tristate. I send clk_2x to CLK and clk_1x to CLK_DIV. (both derived from a...
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16 years ago
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