Field-Programmable Gate Arrays - Page 96

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• 01-17-2007
• Ethernet Interface
• • Surya
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• 5

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• 01-17-2007
• Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use
• • Al
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• 2

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• 01-17-2007
• running applications from external memory
• • rbal
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• 7

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• 01-17-2007
• Clock Frequency
• • psgandhi
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• 2

• 
• 01-16-2007
• interesting article FPGA routing field programmable nanowire interconnect (FPNI)
• • yttrium
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• 3

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• 01-16-2007
• microcode in verilog?
• • Jalen.Ong
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• 5

• -
• 01-16-2007
• Synchronizing four phase-offset clock domains
• • john.windish
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• 0

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• 01-16-2007
• Setup time path on V4 SX w/ IDELAY
• • Brandon Jasionowski
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• 1

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• 01-16-2007
• small, free simple state machine processor suggestions?
• • jonas
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• 5

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• 01-16-2007
• about XAPP028
• • axalay
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• 0

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• 01-16-2007
• Two newbie Chipscope questions
• • kron
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• 1

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• 01-16-2007
• four phase clock using DCM with xilinx FPGA
• • skyworld
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• 7

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• 01-16-2007
• Digital Filter and external PLL (VCO)
• • axalay
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• 4

• 
• 01-16-2007
• Constraining Multiple clock design
• • madair
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• 1

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• 01-16-2007
• Registered?
• • Ian
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• 2

• -
• 01-16-2007
• Verifying a Bidirectional Data Bus
• • pete o.
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• 0

• 
• 01-15-2007
• EDIF format
• • quad
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• 2

• -
• 01-15-2007
• benchmarks for vhdl
• • dhruvakshad
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• 0

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• 01-15-2007
• ISE 9.1i and partial reconfiguration
• • El-Mehdi Taileb
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• 4

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• 01-15-2007
• PowerPC_DDR_controller
• • Vangelis
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• 1

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• 01-15-2007
• How to ensure Select signal arrives after Input signals changed
• • Frai
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• 2

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• 01-15-2007
• How to install xilinx ise8.2 in Madriva linux
• • subint
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• 1

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• 01-15-2007
• Gigabit Ethernet UDP/IP
• • Klaus Falser
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• 5

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• 01-15-2007
• SDK 8.2 error 127
• • Jason
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• 2

• 
• 01-13-2007
• IDELAY and whether pigs can fly...
• • motty
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• 4

• 
• 01-13-2007
• Will FPGAs suit my need?
• • NickHolby
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• 14

• 
• 01-13-2007
• How to get correct initial values from Xilinx Vertex II single port distributed ram with M...
• • Weng Tianxiang
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• 4

• -
• 01-12-2007
• XST bug inferring dynamic shift register
• • Eric Brombaugh
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• 0

• -
• 01-12-2007
• FIFO LogiCore with ISE 8.2 ??
• • Matthieu Cattin
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• 0

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• 01-12-2007
• Stratix RAM limitations
• • Peter Y
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• 3

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• 01-12-2007
• Too many warnings in Modelsim?
• • Frai
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• 2

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• 01-12-2007
• xc3sprog
• • Andrew Rogers
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• 9

• -
• 01-12-2007
• XMD with Microblaze and EDK 8.2
• • Zara
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• 0

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• 01-12-2007
• 16-bit DDR memory controller in EDK
• • sheikh.m.farhan
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• 5

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• 01-12-2007
• user constraint file of slice based bus macro in virtex 4
• • Perry
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• 0

• 
• 01-11-2007
• arbitrator
• • maxascent
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• 1

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• 01-11-2007
• Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
• • Craig Yarbrough
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• 1

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• 01-11-2007
• RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
• • Dale
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• 2

• 
• 01-11-2007
• Xilinx Synchronous FIFOs
• • Brad Smallridge
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• 1

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• 01-11-2007
• picoblaze RS-232 using 62.5 MHz
• • axr0284
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• 5

• 
• 01-11-2007
• Quick question on Coolrunner II IO voltages
• • PeteS
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• 1

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• 01-11-2007
• EDIF generation from C
• • quad
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• 4

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• 01-11-2007
• altera MAX II dev kit LCD mountings??
• • jacko
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• 0

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• 01-11-2007
• Santa Clara Connector and LVTTL etc
• • jacko
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• 0

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• 01-11-2007
• Transport Delays in Modelsim
• • Kevin Neilson
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• 6

• 
• 01-10-2007
• inserting text into a video stream (from a pre-existing video source)
• • wallge
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• 8

• 
• 01-10-2007
• Can I use 3.3V clock into the MGTCLK? MGT RocketIO
• • Dale
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• 4

• 
• 01-10-2007
• LWIP EXAMPLE??
• • Pablo
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• 3

• 
• 01-10-2007
• Is this Multi-Cycle Path ?
• • Ved
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• 1

• 
• 01-10-2007
• VHDL Model of a stepper motor
• • fpgauser
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• 3