Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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warning 1780 shown while synthesis, in xilinx 6.3i
hi I am designing a generic arbiter . while synthesis the xilinx tool is giving warning WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. I...
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16 years ago
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vnavigator problem
Hello all, I am working on merging code coverage results in Verification Navigator from TransEDA. I am encountering an error that I can't seem to figure out a solution for. Has anyone here ever used...
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16 years ago
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Multiple CPLDs on a PCB.
Hi, Apologies if this isn't the best group, but there doesn't appear to be a group. I'm going to start learning about CPLDs to use them in my projects, but the algorithm I've developed will require a...
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16 years ago
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Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables
I have a design that uses a 100Mhz system clock, but only a very small portion actually runs at 100MHz. The rest of the FFs in the design use a synchronous "clk_10M_en" signal which is active for one...
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16 years ago
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Import Xilinx SDK Project in Wind River Workbench
Hello, I would like to know if someone had already used the Wind River Workbench software to debug the PowerPC405 in the FPGA Virtex II Pro ? If yes, how you have imported the Xilinx SDK Project in...
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16 years ago
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ERROR:NgdBuild:604 with user ipcore
Hello, I created an ipcore opb2ip_bridge (with edk's wizard) interfacing the opb and added it to the edk reference design. So far, so good. While running generate bitstream, synthesis stage runs...
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16 years ago
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Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA from Actel with IGLOO power calculator (posted on Actel website). I received very astonishing results. With full logic utilization...
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16 years ago
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Help on OCM BRAM intercafe and assembly code
Hello all:) I am having a problem with the OCM BRAM. I am using virtex II pro and EDK tools. I have an OCM BRAM and the PORT B is unconnected. I would like to give throught a testbench on PORT B data...
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16 years ago
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Help on ocm
Hello all:) I am having a problem with the OCM BRAM. I am using virtex II pro and EDK tools. I have an OCM BRAM and the PORT B is unconnected. I would like to give throught a testbench on PORT B data...
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16 years ago
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GTKWave 3.1.0 for win32
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.0 which supports reload now.
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16 years ago
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[Nios II] How Can I define the pio inputs as a interrupt?
I use the Nios II system to achieve my design. I have define a data bus from the outside of the FPGA, I use a 8-bits PIO ip to connect the signal and the FPGA. I want to achieve the following aim:...
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16 years ago
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Low-level FPGA programming?
Hi. It is possible to have a format of .pof/.sof files from Altera, thus, to decompile some ready projects and try to make our own, omitting Altera software tools?
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16 years ago
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Cannot pass par in tcl, Xilinx webpack 9.1.
Hi, I am learning tcl in Xilinx 9.1. For the learning example watchvhd, the following error occurs. ERROR:Portability:90 - Command line error: Switch "-intstyle" is excluded or already used. What's...
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16 years ago
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Beginning FPGA programming
I'd like to try out some ideas and would appreciate some guidance. Would a 200k-gate FPGA be enough for a simple or complex 8-bit CPU design? I have this Digilent product: but being totally new to...
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16 years ago
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opb_timer interrupt self test problem
Hello there! I ported the WebServer example from MicroBlaze Development Kit, Spartan -3E 1600E Edition to spartan 3e starter kit (revD), it seems to work until I want to open a webpage on the embedded...
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16 years ago
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