Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx System Generator Error!
Hi, I am trying to port my VHDL design code into System Generator "Black Box" with some I/O Buffer instatiated, which is LVDS pad. Where I run through a compilation, the following error appeared:...
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16 years ago
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overloading ' operators in VHDL
Hello, I know that it is possible to overload operators like 'and', 'or', '+',... by using a function with the name "and", "or", "+",... . Is it also possible to overload the attribute operators like:...
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16 years ago
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Opening for Senior Level Design Test Engineer
Hi Friends We are having urgent requirement for Senior Level Design Test Engineer for our client in Bangalore. Job Location: Bangalore. POSITION SUMMARY: We are seeking a talented senior level Design...
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16 years ago
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Urgent requirement for Sr.Engineer (Verification)
Hi Friends We are having urgent requirement for Sr.Engineer (Verification) for our client in Bangalore. Job Location: Bangalore. Senior Engineer (Verification) =B7 Minimum 4 years experience spanning...
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16 years ago
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Excellent Opening For ASIC Design Engineer !!!!!
Hi Friends We are having urgent requirement for Sr. Asic Design Engineer for our client in Bangalore. Job Location: Bangalore. Mandatory Skills: =B7 Minimum 4 years experience spanning all aspects of...
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16 years ago
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Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
I'm trying to do something I think should be simple. I've seen several posts about building custom jtag programmers using byte blaster emulators or xilinx jdrive software, etc. so I hope somebody has...
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16 years ago
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project in chennai
dear friends i have projects for freelance and others contact
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16 years ago
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XAPP851 fifo36 missing
I need the FIFO36 entity for XAPP851 (DDR SDRAM Controller Using Virtex-5 FPGA Devices). Either it wasn't in the zip file or I lost it while unzipping it. Thanks in advance, Brad Smallridge AiVision
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16 years ago
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Ethernet Code Problem with Xilinx Spartan3E
I'm trying to get a Spartan3E FPGA to communicate with a PC. I'm using lwIP and Microblaze and have managed to get the FPGA to receive packets fine, but despite it appearing to bind and connect the...
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16 years ago
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Altera + ARM Cortex-M1
Could we expect the same step from Lattice? Or Xilinx will come with this possibility sooner?
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16 years ago
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VHDL Design Pattern Book
After reading started to wonder if anyone has attempted to write a book on VHDL design patterns. Or for that matter HDL patterns in general. I guess I am looking for something in the same style as...
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16 years ago
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precision errors. microblaze vs matlab single precision... huh?
Hi all embedded gurus out there, I am working on an embedded platform using microblaze. I am trying to implement an algo, which does a inverse matrix function on the microblaze (via C) and then port...
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16 years ago
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Command line quartus_pgm very slow
Hi folks, I have a question regarding the use of the command line quartus programmer tool under Linux. I have been using for a while, and I noticed that this latter one was *very* slow (10x) compared...
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16 years ago
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[Nios II] How fast the cpu in Nios II can reach in the Cycone ?
Can it reach 100 DMIPS =A3=BF I give the cpu 100MHz clk, and use the Fast Core. There is a program: void main() { while(1) { IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, data++); } } The frequence of...
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16 years ago
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ML410 Board & 1GB DDR2 DIMM Problem
Hi - I'm having problems getting a 1GB DDR2-667 DIMM to work with an ML410 board. I'm working with the plb_ddr2 IP core in XPS. The auto- generated memory test works perfectly with the 256MB DIMM that...
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16 years ago
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