Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Beginner Advice (Languages, tools etc.)
Hi, Please excuse me for sounding like I don't have a clue what I'm talking about. I am here because I want to learn. I have a project I have been working on that requires physical hardware. I will be...
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16 years ago
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Learn About High-speed Serial Connectivity & FPGAs - for FREE
Hello: One-day seminar on High-speed Serial Connectivity & FPGAs at multiple locations in the USA. Free sign-up, discounts on development kits. Register at Thanks -Navneet
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16 years ago
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add_file -verilog +define ..... filename.v
Hi, I have a question on Synplicity synthesis / FPGA synthesis. Is there a way to give in the `defines from the command lines in synplicity synthesis .. something like add_file -verilog +define ........
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16 years ago
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post translate and post PAR problems with XST and Modelsim
I am trying to do a Virtex4 design, I have completed the post synthesis (XST) simulations in Modelsim - everything appears fine. When I run the PAR and simulate the generated model. I get all zeros on...
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16 years ago
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Spartan-3E Slave Serial Configuration
Hi All, I'm designing a circuit for configuring 4 Spartan-3E FPGA from an Atmel AVR microcontroller. I want to configure the FPGA in slave serial mode. Because of the difference in the supply...
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16 years ago
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Physical Design Contribution to FPGA/CPLD success
CPLDs and FPGAs both make (or made) use of "non-standard" implementation of digital circuits, namely wired-OR and pass-transistors. Both techniques are much more difficult to use in standard cell...
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16 years ago
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Xilinx GSRD reference design and 3rd party synthesizer
Hi all, I'm wondering if anybody synthesized the Xilinx GSRD reference design with any 3rd party synthesizer. I'd like to compare the fitting report with the one produced by ISE. Anybody can help me?...
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16 years ago
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Is post-place and route simulation useful?
Hi, Is the post place&route simulation so important? IMHO doing post synthesis (or post translate) simulation for verifying behavior than doing a post place and route static timing analysis is...
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16 years ago
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Open-Source VHDL Synthesis for FPSLIC?
Hi All, I've been doing some development work over the past year or so on the Atmel FPSLIC platform. I've run out of time on the license for the Mentor software that came with the dev kit, and am...
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16 years ago
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Virtex-4 PCB design
Xilinx posts gerber file in *.pho format on their website for all of the evaluation boards. Does anyone no how to import these into cadence OrCad? or what tool they used to design them in? Thanks,
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16 years ago
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MicroBlaze Tutorial
Can anyone suggest a tutorial for MicroBlaze? I have googled it and found many tutorials, however, most seem to emphasize the software end of things, whereas I already have an evolved hardware system...
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16 years ago
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Problem with Microblaze max clocking
Hi everybody, I'm using EDK 9.1i and in my design I use a Microblaze core (v 6.00.b). The device is a xc2v1000-4 (in a 2VMB1000 board from Memec Design). In every system that I create, the maximum...
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16 years ago
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genmcs.pl for a V4FX60 aka loading the cache from the prom on a multi processor device
I have used for single processor implementations but I have had no success in a multiprocessor device. My design runs perfectly through gdb/xmd but when I try and build the mcs file to allow it to...
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16 years ago
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Virtex5 PLL for DDR2 interface
I used the ISE 9.2 MIG to create a DDR2 mem controller for 267MHz memory chips, and it included a DCM to generate the 267MHz clock at 0 and 90 degrees, from an external 267MHz input. In my app, I have...
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16 years ago
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Peripheral Trouble!
Hello, I am using the xilinx virtex II development board xupv2p. I have built a expansion board that connects to the high speed expansion port, an delivers information from a camera. In ISE, I have...
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16 years ago
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