Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Using PlanAhead for Partial Reconfiguration
I have a doc. named "Partial Reconfiguration Design with PlanAhead 9.2" and use PR_V5_DVI.zip for example. While following the step to Implementing the Static Logic and Implementing the PR Modules,...
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16 years ago
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how interfacing of cpld and cpu done?
please give me information about inerfacing of cpld xc9572 & cpu
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16 years ago
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hardware software codesign
Hi there I am a newbie to FPGA based development. So I have a Xilinx II board. What I need to do is basically implement an algorithm on the board and then use a linux based application to give the...
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16 years ago
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Comparing Adder synthesis techniques
Hi, I am working on a study to copmpre the effiency of synthesied adders. I have built a ripple adder and a carry look ahead using VHDL for a Virtex FPGA. I know that the lookahead carry adder is much...
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16 years ago
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DMA scatter gather with PLB bus?
Hi everyone. I'm trying to transfer data from DDR memory to a custom PLB_IPIF peripheral in a Virtex II Pro XUP card. I have some questions: 1. In EDK is not possible to configure a scatter-gather DMA...
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16 years ago
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Is it possible for two wires to share the same FPGA pin?
For example, I have two wires FA[23:1] (address line for Flash) and RAM_A_SD[63:0] (data line for SRAM), due to the number of pins constraint, FA and RAM_A_SD share the same FPGA pins (seen from...
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16 years ago
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proasic plus. actel
thanks Thomas Stanka! But... In my code I have instantiated a GL Buffer (is a fast clock). But in the synthesis: the log say... Automatic dissolve during optimization of view:work.w_r9(w_r9) of...
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16 years ago
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Multi-cycle paths in VHDL libraries
Hi everyone, may I ask you a question. I'm trying to find out how to handle multi-cycle paths in VHDL libraries. I'm using Xilinx ISE 9.2i and XST. I have designed a number of modules, all compiled...
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16 years ago
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Gated Clock Problems
Hi everyone, I am running into a really peculiar problem for a research project that I am working on. The circuit is fairly simple one, which needs to measure which one of two signals reaches a...
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16 years ago
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help! ACTEL PROASIC PLUS clock buffer
Hi!, I have a big problem: I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global pin (4 GL macro), I need put a clock in a global buffer but I can=B4t because I have others signals...
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16 years ago
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FPGA history
Hi all, for my PhD thesis I am looking for a citeable publication describing the FPGA technology advances during the recent years (say 10 years - or even from the very beginning), especially what...
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16 years ago
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Population Count circuit
Out of curiosity: I am currently studying some problems which require many population- count operations ov various sizes. I have used population count in a course I taught last year, as it can...
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16 years ago
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Verilog simple dual port memory with different input and output widths?
Has anyone got any example Verilog code for this? I'm currently using Quartus wizard generated code and wrapping it up in a Verilog module so I can use my own parameters instead of running the wizard...
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16 years ago
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Looking for fast AES cores with low latency
Hi, Since the initial rash of AES / Rijndael cores a few years ago, I haven't seen much research at the high speed end. Does anyone know how low the latency is for a recent high-end core in a current...
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16 years ago
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Data-side BRAM
Hello All, there is a 32bit Data Bram. I am trying to load a 32 bits data in the fourth location (4) of the Bram (0-255 locations). The addresses are : Address Map for Processor ppc405_0...
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16 years ago
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