Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Automotive Electronic Control
Hi, I'm looking for a control unit (plc, control card, control module) for construction equipment (excavator). It should contain digital and analog inputs and digital outputs. Any body have experience...
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16 years ago
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partial reconfiguration, par error
When I implement the reconfigure module, after ngdbuild, map and continue with par there show some error but look like the same thing. Did I place the busmacro in wrong place? My environment is...
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16 years ago
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[ANN] FPGAOptim - Do you know where your slices are going...?
Hi all, I now have the opportunity to make available to the wider world an internal tool I developed to focus my area-optimisation efforts. It simply displays the hierarchy of your design, sorted by...
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16 years ago
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BRAM bytewide write enable problem
I have created two BRAM using coregen (BLK_MEM_GEN_V2_4) , out of them #1 is not supporting byte enable #2 supports byte enable Both of them are of same size 512x32 Now, during simulation the read...
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16 years ago
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ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias
Hello fellow developers, users and friends This is a list of free (some of them GPL'ed) tools that I have written over the course of the few last years. You can access and download the tools from:...
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16 years ago
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Xilinx GTP based serial link
Hi everyone, I am investigating about the best communication link protocol for my high throughput data link. I am required to support >= 2.0Gb/s average transfer rate and one way only optical cables...
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16 years ago
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Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation, and Optimization" ?
Greetings, Have any of you read Steve Kilts' book "Advanced FPGA Design: Architecture, Implementation, and Optimization"? If so, I'm interested in your opinion. I consider myself an intermediate level...
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16 years ago
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FREE BACKGROUND CHECK
Why pay for an expensive background check when you can conduct your own for absolutely free. Check it out at Check it out
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16 years ago
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CRC calculation of Virtex 4 bitstream
hi. i have to calculate the crc checksums of a virtex 4 bitstream. there are two ckecksums: one direct after the configuration frames and one at the end of the bitstream. no i want to know, if all...
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16 years ago
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Does Modelsim work under Windows Vista?
Xilinx's ISE 9.2 now supports Windows Vista (32-bit only.) Do other tools like (Mentor Modelsim and Xilinx XPS/EDK) run under Windows Vista?
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16 years ago
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Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?
I've looked through Xilinx's website, but I can't determine whether the embedded 10/100/1000 gigabit MAC is supported in the EDK. The reference designs and various appnotes only cover the embedded...
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16 years ago
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Answer: maximum number of state machines in a current chip: > 500k
Hi, Here is the answer to the maximum number of state machines in a current chip: > 500k. My original answer posing has some errors. 1. It is L2 cache that uses a lot of state machines; 2. IBM/Intel...
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16 years ago
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DDR RAM timing contraints
hei list, i am working on a DDR-Ram controller for the ml401 board from xilinx. the controller i am using is generated by the MIG tool provided by xilinx. I have adapted this design to be used with...
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16 years ago
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Configuring Impact on any version of linux
Hi guys i want to use Xilinx 8.2i or 9.1i or even 7.1i for burning codes on my FPGA board using the Parallel port on Linux..The linux which i have are Fedora Core 6,Ubuntu and Open Suse 10.2..I have...
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16 years ago
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Enterpoint Web Site
For those of you frustrated with our PayPal payments system we have hopefully now got it sorted. Any more problems please let us know. Apologies to those that suffered. We are also hoping to offer...
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16 years ago
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