Field-Programmable Gate Arrays - Page 105

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• 11-23-2006
• C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
• • Alfmyk
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• 2

• 
• 11-23-2006
• query
• • ram
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• 2

• 
• 11-23-2006
• Altera configuration with microcontroller
• • Nevo
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• 4

• 
• 11-22-2006
• Division of a (rather large) Gate level Combinational Design
• • olson_ord
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• 4

• -
• 11-22-2006
• Cache trouble in XPS
• • Rune D. Jørgensen
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• 0

• -
• 11-22-2006
• Cache trouble in Xilinx XPS
• • Rune D. Jørgensen
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• 0

• -
• 11-22-2006
• Aurora and Chipscope
• • nana
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• 0

• 
• 11-22-2006
• Virtex 4 Internal Tristate (BUFT)?
• • Koen Van Renterghem
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• 2

• 
• 11-22-2006
• Xilinx EDK - using EMC with Intel Strata Flash - assistance needed
• • guybye
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• 1

• 
• 11-22-2006
• Xilinx DDR2 IP core performance
• • Antti
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• 1

• 
• 11-22-2006
• Protecting netlist for Xilinx
• • Sylvain Munaut
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• 8

• 
• 11-22-2006
• ISE 8.2 & XC9500XL family
• • Jozsef
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• 3

• 
• 11-21-2006
• CORDIC FM Demodulation
• • ma
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• 8

• 
• 11-21-2006
• I2C "READ" Setup/Hold Requirement
• • markus
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• 2

• 
• 11-21-2006
• Spartan 3E-Kit
• • spartanius
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• 13

• 
• 11-21-2006
• V5 LXT PCIe Block simulation
• • sovan
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• 1

• -
• 11-21-2006
• Spartan-3E Starter Kit and programmable pre-Amplifier
• • GaLaKtIkUs™
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• 0

• 
• 11-21-2006
• timing constraints
• • ram
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• 2

• 
• 11-21-2006
• What's wrong with my tcl example in Quartus?
• • fl
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• 2

• -
• 11-21-2006
• Missing module : XFFT_V3_1 Verilog (not VHDL) module
• • Vitaliy
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• 0

• 
• 11-20-2006
• Spartan 3 Starter Kit .mcs upload problem
• • Jürgen Böhm
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• 1

• 
• 11-20-2006
• DDR_SDRAM_VHDL_models
• • Vangelis
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• 2

• 
• 11-20-2006
• DDR_VDHL_models
• • Vangelis
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• 3

• -
• 11-20-2006
• ISE Synthesize Properties box
• • Roger
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• 0

• 
• 11-20-2006
• Parallax Stratix Smartpack accessories?
• • radarman
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• 1

• -
• 11-20-2006
• Differential to single ended convertion in FPGA
• • prathap.ap
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• 0

• 
• 11-20-2006
• Spartan3E price update ?
• • tullio
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• 3

• 
• 11-20-2006
• Need examples/instruction: use of altpll_reconfig (Altera)
• • Bob
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• 3

• 
• 11-20-2006
• Simple questions on IDELAYCTRL
• • lecroy7200
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• 18

• 
• 11-20-2006
• Input setup time & Hold Input
• • jajo
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• 1

• 
• 11-20-2006
• Q on duty cycle
• • bhavanireddy
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• 1

• 
• 11-20-2006
• false path
• • gen_vlsi
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• 1

• -
• 11-20-2006
• query in delay chains
• • kumar
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• 0

• 
• 11-20-2006
• Spartan-3E slice resources
• • kunil
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• 4

• -
• 11-19-2006
• Virtex-4 DDR RAM Usage (with VHDL)
• • Elmar Weber
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• 0

• 
• 11-19-2006
• spartan-3e starter kit and ethernet
• • hakan.aydin
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• 2

• 
• 11-18-2006
• Re: board - T562.jpg   [ 2 3 ]
• • John Larkin
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• 46

• 
• 11-18-2006
• EDK 8.2 Block RAM error
• • Antti
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• 15

• 
• 11-18-2006
• master support for OPB device
• • get2venu
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• 1

• -
• 11-18-2006
• IDELAY setup/hold
• • Tom
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• 0

• 
• 11-18-2006
• Static Timing Analysis vs Dinamic Timing Analysis
• • jajo
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• 1

• 
• 11-18-2006
• Input setup time & Output valid delay
• • jajo
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• 1

• 
• 11-18-2006
• IDELAY Calibration - Virtex 4
• • Trevor Coolidge
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• 4

• -
• 11-18-2006
• Re: PCB Design Houses
• • Trevor Coolidge
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• 0

• 
• 11-18-2006
• query in a design
• • kumar
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• 1

• 
• 11-17-2006
• state problems with Quartus II 6
• • Frank Buss
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• 2

• 
• 11-17-2006
• PCMCIA interface
• • vasile
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• 7

• 
• 11-17-2006
• How could the 'Serial write time out' happen
• • ZHI
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• 4

• 
• 11-17-2006
• pulse jitter due to clock   [ 2 ]
• • Al
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• 31

• -
• 11-17-2006
• ML405: Board support package
• • Gerd
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• 0