Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
UCF Constraints: drive and slew
Hi, I need some help in this design: I use a design in which I have detected some skew problems. I have seen the archive.ucf (with the constraints), so "slew" and "drive" properties are used in some...
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FPDP to PCIe
Hi Everyone, Are there any hardware modules that I can buy to convert a data stream (serial FPDP over fibre) into PCI express and connect to a PC using the PCIe port? I have not been able to find a...
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Bug in Synplify?
Hi, I have a behavior in Synplify Pro for Actel Fpgas I would call a bug (seen in each old version I could find up to the newest 9.0) If having a register file which is accessed only in words with...
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Basic questions about the Nios II.
Hello. I'm getting a better outline of what's available and the differences between the different options, such as FPGAs and CPLDs. Although, I've just come across Alteras "Nios II Embedded Processor"...
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Stratix GX
Can anyone help on finding a home for the Altera Stratix GX chips. I am in a situation where one of my contracted accounts has purchased the Altera Stratix GX product prematurely. They are not going...
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Inferring wide adders comprising multiple DSP48s
Is it possible to infer wide adders that require multiple DSP48s? In my experiments with Synplify, I found that it will infer a DSP48-based adder when the inputs are up to 36 bits wide, but when I use...
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YARDstick custom processor design tool homepage updates
Hi friends i've just made some updates on the YARDstick website: A summary of the updates: 1. Overview section 2. Screenshots section 3. A0-size poster that was used for presenting YARDstick at the...
 
Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
Altera claims to have a snazzy early power estimator that needs MXCOMCT2.OCX. I wonder if anyone has managed to get this solution to work? I spreadsheet works (did not have to use the fix) on my...
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XST corrupts my state machine. Only disabling FSM encoding helps
Hi, i have a state machine like this always @( * ) case(state) IDLE: casex(SOME_STATEMENTS) {inputs}: next = NEXT_STATE1; {inputs}: next = NEXT_STATE3; default: next = IDLE; STATE1;...
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Very basic clock questions.
Hi, I'm making my way through the Virtex 4 user guide trying to get to grips with FPGAs, although I'm only a few pages in and already have a few questions: - Why are there 32 global clock lines for a...
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Logic minimization software with LUT6 support?
I am looking for open source software for logic minimization (a la espresso) targeted to a lookup table based architecture that can take advantage of six inputs LUTs (as you can imagine I have in mind...
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Own soft-processor
Just interesting, how often some company is able to develope their own RISC soft-core processor for their needs, without any need to publish that fact or reveal any details?
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How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
All I can find is a one-page specification of "Kingston KVR100X64C2/128", but I do not know about the input and output interface of this SDRAM, e.g., what are the input and output signals, and how the...
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Never buy Altera!!!!
Ordered a license for Quartus a month ago. Order is processed, rep says she needs NIC ID and host ID from PC, we explain that a new PC is on order and we will need to license software to old machine...
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Variable Phase Shifting for VirtexII DCM
Hello, i have a problem with my dcm modules. By changing of frequency the clock-out phase gets also changed. So I have found a xapp from xilinx which may help me (Active Phase Alignment xapp268). I...