Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
FPGA tools under VMware or Parallels on a Mac?
Which vendor's FPGA development and USB download tools have people found to work reliably on a Mac or MacBook under either the Parallels or VMware virtualizers, running Windows XP, 2k or linux? If so,...
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Cyclone II SSTL-2 on-chip resistors
Hi, I'm trying to build a board that will use a DDRAM PC2700 memory module connected to a Cyclone II FPGA. It uses SSTL-2 signaling, and one thing I really don't understand is why the on-chip series...
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HELP, how to time constraint part of a design?
Hello Could someone tell me how to make timing constraints in a particular part of a VHDL design? Inside my design I have an enity that makes a calculation. That entity I can clock at about 50 MHz...
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What happened to Confluence and HDCaml?
It seems that the launchbird site has disappeared. I had heard that Confluence was superceded by HDCaml, but it looks like that site is dead as well. I'm currently learning OCaml and would like to...
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Compiler Options
Hella all:) I would like to ask for the complier option in the XILINX EDK. I have written ans inline assembly code. and simulation in Modelshim. When i am compling the code i said "No Optimization"....
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Unrouted nets (Xilinx FPGA Editor)
Hi all, I meet some problems in the P&R process of my design. The Place & Route Report shows the following messages. Because it stoped at Phase 6 for a long time, I paused it and it shows there's 1...
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Quartus-II 7.2 web-edition Systemverilog improvements
Quartus-II 7.2 has improved upon Quartus's Systemverilog preprocessor: `define SET_REG( x, y ) reg_``y
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Xcell Article on 1.2Gsamples/sec FFT
Hi all, Just read an interesting article in Xilinx's xcel publication. Lots of technical detail, and no "marketing" to speak of. After reading this I had a couple of burning questions I'm wondering if...
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Timing Constraint Question
I am working with an EDK design that utilizes an MPMC2 core. There are several clocks associated with this core. All of the clocks are created using DCM's and inverters. I am failing timing b/c cross-...
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Legacy support of a Max 7000S
Group, I have the need to copy a Max 7000s device that was originally developed under Max+Plus II. I am not able to locate the original project file (my bad) but I do have a working device that I can...
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DDR DIMM clock distribution
Hi I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM. And I'm wondering how to distribute clock signal. DIMM has 6 clock signals (3 differential pairs). I figure out two solution: 1. Use...
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8B/10B Xilinx Paper
Hello newsgroup, I am trying to understand the Xilinx reference design (XAPP391: Design of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)). When performing the functional simulation (which is...
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code coverage in modesim se 6.1f
hi , how can i save the coverage data , so that the output file contains the missed coverage lines and/or coverage lines and how to merge that files so that the final output file contains missed...
 
CY22393
I need info about programm FLASH without external programmer.When I program this IC from I2C I rpogramm volatile configuration memory?
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Need suggestion on FPGA kit
Hi friends I am working in a pvt concern.We are decided to purchase FPGA trainer kit. But we are confused with Xilinx-Virtex-5 and Altera-stratix-3. Which one will be the better in configuration?...
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