Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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LEDs, buttons and LCD
Hello folk! Hello, I have just bought Spartan 3E-1600E Microblaze Development kit and I am complete beginner. Really want to learn FPGA programming but have no idea what this board is for. For...
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16 years ago
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FPGA input level conversion
+----------* +3,3V output --- | | R=66 ohm | | --- | ---- / CDBU00340 or similar Vf=0.6 / ---- | FPGA +2,5V input *----+ GND *---------------* GND Is it possible to use the above construction to adapt...
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16 years ago
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mess around with supply voltage to cyclone III
Hi, I have a Cyclone III FPGA. I have created a circuit on it whose performance I want to observe under the influence of supply voltage variations and glitches. I want to create intentional glitches...
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16 years ago
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Re: Wishbone Specification in Action
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16 years ago
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Error using SOPC builder - "Custom SDRAM" with 8-bits gives error with Signal "az_be_n"
I'm trying to make a SDRAM controller with SOPC builder, but when I change the data width to 8bits I get the following error.. Warning: Signal "az_be_n" of type "byteenable_n" and width 1 must have...
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16 years ago
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Fast Sampling of digital signals
Hi, I'm building a S/PDIF Receiver for implementation on spartan 3 fpga. I don't have an expensive DSO to analyze the spdif signals : ( So i decided to build a sampler and run it fast enough, say...
7
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16 years ago
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FPGA pin swapping utility
We are using V5LX110T and V5L330 FPGAs. Are there decent pin swapping utilities so that we do not have to spend a lot of time in PCB Laout to do the pin swapping? I am hoping that the tool shows the...
6
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16 years ago
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VHDL trivia?
Hi folks! A bit of VHDL trivia. What I want is the reverse of: one_hot_gen: for i in 0 to 15 generate begin one_hot(i)
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16 years ago
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Dynamic Reconfiguration books
Hi everybody! I would like to get advises about good books in dynamic reconfiguration using FPGAs. I need theoretical (algorithms, methods) as well as practical information. Thanks in advance
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16 years ago
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xilinx Edititons
Hello all, I would like to ask if i can install in my computer 2 different versions of EDK, one older than the other. O/S : Windows XP regards xenix
4
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16 years ago
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What to consider for source synchronous clocking?
Hi everyone, pardon me but I'm pretty new to this. I'm using a Spartan 3 right now, and I'm trying to provide source synchronous clock clocking to a SDR SDRAM using DDR register. The component looks...
3
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16 years ago
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systemc thread processes are called with the same thread in windows
i observed that all processes registered with SC_THREAD macro are called with the same thread. Is this correct? In my module im having a infinite loop inside the process which reads from a port...
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16 years ago
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difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
Hi alls, I've a question which seems stupid, but I don't find answer anywhere.. ( maybe I don't search correctly ) What is the difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES ? I don't...
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16 years ago
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FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
Hi ho here is code process (m_sck) begin if (m_sck'event and m_sck=3D'1') then do64(62 downto 0)
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16 years ago
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Reason for LUT1_L buffer insertion in Synplify EDIFs?
When generating EDIF from Synplify, I frequently notice buffers (LUT1_L primitives with INIT property of 2) inserted in the circuit. Does anybody know why the tool is doing this and/or whether it can...
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16 years ago
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