Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Programming Atmel dataflash with xilinx impact
The Xilinx Spartan-3E can be configured from an Atmel SPI dataflash. This dataflash can be programmed with a download cable and the impact tool. From what I can find in the tool and docs it is only...
2
|
16 years ago
|
2 | |
|
|
Addresses of subsystems
Hello All, I have a system which consists of many subsystems which will be connected to a common bus (this includes 16-bit data and 16-bit address buses). This system is FPGA-based and I want to...
11
|
16 years ago
|
11 | |
|
|
XPS FIFO PLB device problems... (verilog)
Hi all, I'm trying to develop a core that is connected to the PLB bus and uses FIFO to communicate to the PPC. The FPGA I'm using is a virtex2pro on a XUP board. When I go through the process to...
—
|
16 years ago
|
— | |
|
|
Which demo board
Hello all, I need to develop a broadcast application using FPGA, but I am new to FPGA. I thus consider buying a demo board. At least, I need 1 SDI output and 1 SDI input, 1 Gigabit Ethernet port, and...
—
|
16 years ago
|
— | |
|
|
Nios II, ThreadX, NetX Anyone?
Hi, I'm looking for a very compact TCP/IP stack for the Nios II, and the ThreadX/NetX combo seems to be, at least on paper, the smallest. Anyone using this combo? How small are you able to build it,...
4
|
16 years ago
|
4 | |
|
|
Nios II, ThreadX, NetX
Hi, I'm looking for a very compact TCP/IP stack for the Nios II, and the ThreadX/NetX combo seems to be, at least on paper, the smallest. Anyone using this combo? How small are you able to build it,...
2
|
16 years ago
|
2 | |
|
|
Changing refresh rate for DRAM while in operation?
Hi, I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera DE2 board. I've gotten the hardware interface squared away (thanks everyone for your help!). Now it's the tricky stuff. Any...
50
|
16 years ago
|
50 | |
|
|
Alter RBF Compression
Hi, Does anyone know which algorithm or scheme is used by Quartus to compress FPGA configuration files such as SOF or RBF (raw binary file)? Thanks, Jason
6
|
16 years ago
|
6 | |
|
|
ISE or EDK?
Hello, I want to design a system which includes ADC, digital filter, DAC with dataflow chart like this: audio_signal1->ADC->digital filter->DAC->audio_signal2 digital filter has to be controlled from...
3
|
16 years ago
|
3 | |
|
|
microprocessor on fpga problems
Hi, Just wondering what could go wrong when synthesizing memories (i- cache, d-cache, and write buffer) of microprocessors on fpga Xilinx Virtex 5? Thanks! Wei
7
|
16 years ago
|
7 | |
|
|
Building a Huffman codebook in VHDL
Hi, I've been looking at available VHDL/Verilog implementations of huffman coders. It appears that all currently available implementations use a fixed codebook (e.g. the one specified in the MPEG...
3
|
16 years ago
|
3 | |
|
|
DVB-T/H help me ?
Hello, excuse me for my not perfect English. I must begin a project for the realization of the DVB-T/H modulator. I am documented a lot, using also the specific ETSI, but I have some question without...
—
|
16 years ago
|
— | |
|
|
virtex-4 power consumption
Now I have ported a design from virtex-2 to virtex-4,because the xilinx announced virtex-4 have a lower dynamic power,but actually when I finished my design,running the same design with virtex-4,the...
1
|
16 years ago
|
1 | |
|
|
xilinx 3adsp starter kit : where are demo and reference designs ?
hi groups xilinx docs is rather thin (ug454) ... is there somewhere an ucf file, and some public reference design (microblaze) thanks, raph
—
|
16 years ago
|
— | |
|
|
Files produced by Quartus II compiler
Hi, I'm a student using Altera Quartus II v6.1 to program a Cyclone II on a DE2 development board. I'm starting to build a library of Verilog modules to re-use in future projects (mostly simple things...
3
|
16 years ago
|
3 |