Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FPGA vs ASIC
When it comes to designing for fpgas or asics there are a lot of guidelines/rules that need to be followed consistently between the both. Yes! things dealing with verilog event queue, metastability...
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16 years ago
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"SPI indirect" programming for any FPGA/CPLD
Hi attached to xilinx forum message is a simple JTAG-SPI gateway IP core that is been used for SPI flash programming on S3E the demo toplevel include Spartan-3 BSAN, but by only replacing that...
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16 years ago
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Power supply filter capacitors
I'm woefully undereducated to be doing this, but I figure the best way to learn is by doing, so I need a little help with my current project. I'm designing a lighting dimmer around the Altera Cyclone...
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16 years ago
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Question about the clocks power in XPower.
Hello, All, T the clocks power results given by the XPower are always 0 when I tested my designs. But there must be some clock power consumption. If an EDK generated project which contains a...
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16 years ago
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fgpa beginner
I'm a beginner with FPGA and I want to dive into the digital video filtering, analysis and display. I can clearly imagine that it is a big performance for a beginner and I wonder to start in the...
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16 years ago
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ISE PACE Question
HI, I have a Xilinx ISE - PACE editor question- I am using the schematic editor for now just to get familar with the tools and the fact I don't understand a HDL yet. What Iam trying to do is very...
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16 years ago
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compile EDIF(generated by Celoxica DK4) using Quartus II
Hi all, I got an error when I compile the EDIF file generated by Celoxica DK4. The code is written in Handel-C. I add the EDIF file and the TCL file generated by DK4 to the project, the error is...
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16 years ago
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Signetics N82F101F
Hello all Does anyone have a Signetics data sheet / data book with this part? Thank you
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16 years ago
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is Quartus 7.1 really that S*** !?
Hi so far I hear that "Altera tools are getting better" - now I wonder how long should one wait til they become useable? Q II 7.1, very small design for smallex MAX2 Quartus will self-terminate every...
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16 years ago
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xilinx spi flash programming
I'm about to place an SPI flash for spartan 3e but I'm a bit disapointed in having to place another header to program it via impact. It would seem that a fairly simple piece of code could configure...
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16 years ago
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builing a SPI interface in vhdl
HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let an fpga read and write a flash memory. The fpga is a Xilinx Spartan3E, while the memory is an ST M25P16 (serial I/O). Do you know...
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16 years ago
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MPMC2 NPI Help!
I am using the MPMC2 to implement a PLB and NPI port config. The PLB port works as expected. However, I am simulating my design and the NPI isn't working as I expect. I have created a small NPI...
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16 years ago
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Paper about selecting fixed point bit widths?
Hello all, Can anyone point me to a good general purpose paper about selecting appropriate bit-widths for a fixed point implementation of a signal processing algorithm? I've looked around and haven't...
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16 years ago
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MGT
Hi all, I am trying to use a Aurora Core and MGT transceiver to get high Speed serial transmission signal out. I have run into several problems.. One problem is getting the Aurora Core simulated... I...
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16 years ago
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Multilinx and chipscope
Hi all, I've got a question about Multiplinx ( USB/JTAG interface) and ChipScope Pro. I'm using ISE 9.1i and I would like to use chipScope Pro to debug my design but it seems that multilinx platform...
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16 years ago
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