Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
Hi FPGA Group! I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM interface, generated with the Xilinx Memory Interface Generator. The complete system consists of a PCI interface, an I/O...
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16 years ago
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registers are not shown in waveform (xilinx microblaze)
Hello fpga community I try to compile a testbench in order to observe the waveforms of the registers of microblaze. The problem is that i cannot see any set of MicroBlaze register waves (32 assigned...
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16 years ago
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Is it possible to check how cache memories are mapped to FPGA block rams?
Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems that the cache memories of the processor are not behaving correctly and I have to turn off the caches for application programs to...
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16 years ago
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2 FPGAs /w programming FLASH in one JTAG chain
Hi there, currently I am designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. It should be possible to program them with onboard Xilinx Platform FLASH PROMs as well as via JTAG with the...
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16 years ago
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How to make sure processor memories have been correctly mapped onto block ram on fpga?
Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems that the cache memories of the processor are not behavioring correctly and I must make sure that the caches are turned off for...
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16 years ago
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FPGA Configuration
Hello VLSI Engineers. Its is true that FPGA boots its program from an external PROM. How external eproms are connected to FPGA. Is there any requirement in making PCB with FPGA. Thanks
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16 years ago
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Final CFP: 2008 International Workshop on Multi-Core Computing Systems
*********************************************************************** EXTENDED PAPER SUBMISSION DEADLINE: November 20, 2007 ***********************************************************************...
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16 years ago
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Xilinx xflow for the ISE Quickstart Tutorial project?
Hi I've gone through the ISE Quick Start Tutorial and can get its 4 bit counter downloaded and working on a Digilent board with an xc3s200-4ft256. (BTW: the Quick Start Tutorial is located at My...
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16 years ago
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HPCNCS-08 Call for papers
The 2008 International Conference on High Performance Computing, Networking and Communication Systems (HPCNCS-08) (website: ) will be held during July 7-10 2008 in Orlando, FL, USA. We invite draft...
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16 years ago
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total equivalent gate count
Hello all, The ISE map report gives out a figure under the heading total equivalent gate count... So can anybody help me in understanding what exactly it means?How can we relate it to the ASIC gate...
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16 years ago
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Selecting I/O pins
Hi, I was recently asked in an interview that what points you will consider while selecting the I/O pins in FPGA ? One thing which came to my mind was : 1) considering board aspect that the pins...
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16 years ago
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Bitfile checking
Assuming a scenario that I have a bit file built for a particular FPGA, but i don't have a that FPGA device to download it to, Is there a way to check it works on that particular FPGA? Thanks in...
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16 years ago
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How to use an internal signal in a testbench...
I am simulating an EDK system and want to use some internal signals at the testbench level (without routing them up to external ports). I thought that you could simply do this by assigning signals...
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16 years ago
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Re: Xilinx Isolate circuitry
What do you mean by "sensitive circuit"?
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16 years ago
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XMD with CableServer OR remote EDK solution
Hi, Is it possible to run XMD remotely using CableServer? This is the only missing item that would enable me to work completely remotely from my desk (instead of being in the lab, where we can't drink...
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16 years ago
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