Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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can i use dual edge or two clocks?
My FPGA master clock is at 100MHz. I have assigned a counter to count from 0 to 99 to achieve a period of 1usec. As the counter is counting from 0 to 99, i will take 1 sample at each count and...
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16 years ago
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Digilent V2P Board
Using the Digilent XUP V2P Board, I have to use additional memory (256 Mb DDR SDRAM). The only memory drivers I can find run with the embedded processor kit. I do not wish to use the PowerPC or...
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16 years ago
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Spartan-3E display developpement kit
Hello, I 'm trying to use the Spartan-3E display developpement kit. I can program the FPGA with JTAG ( in direct), and the PROM (XCF 08P) with JTAG ( But after an On/OFF, the FPGA is not programmed...
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16 years ago
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Re: Ping Jim: The PFD is dead!
I "invented" this last week. FPGAs aren't very good at implementing the classic charge pump. The outputs here are just hard (not tri-state) logic outputs, driven directly by the up/down flipflops in...
8
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16 years ago
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Capability of a FPGA device.
Hi, For a future project we are considering the use of FPGA technology and IP cores instead of using an ASSP solution. As a software guy...only doing some initial invistigations I have absolutely no...
7
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16 years ago
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xilinx bmm file problem
hello, Has anybody experience with xilinx bitfile merging using a bmm file? I've a small processor core running in a spartan 3A using romcode which I install into a generated vhdl file. like entity...
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16 years ago
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ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
Hi, I want to make a simulation. However, I get an error like below. I dont know how to solve this problem. does anybody have an idea about this problem? THE ERROR: Running Fuse ... Compiling vhdl...
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16 years ago
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Is it possible to debug a vhdl design over jtag?
Hi, I would like to debug a vhdl design over Jtag. Is it possible?. As XMD for EDK but for vhdl code. My best regards Pablo
7
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16 years ago
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7 | |
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Weird behavior : Altera DE2, C++, For loops, SRAM
So I've implemented a NIOS II board using the SOPC builder. I ran out of on-chip memory so I went off-chip to the DE2's SRAM. Suddenly my programs stopped working and the for loops has an unusual...
1
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16 years ago
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debugging ppc + mb
Hi all, I would like to debug a system containing a microblze and a ppc405. I'm using the xmd (gdb) for both of these units. I have a single mdm unit and a jtagppc (a single jtag interface). Is there...
4
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16 years ago
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Updating my bookshelf
Hello all I am looking for references of books about digital design (ASIC & FPGA, high speed, processor, signal processing ... ) What are the books you wouldn't work without ? Thanks in advance...
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16 years ago
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X3100A design with Synplify 8.8 and foundation 1.5 possible?
Hi foundation 1.5 mapper terminates on windows XP with GPF fault, i wonder if it is caused by incompatibility with winXP or maybe the edif file generated with synplify is somehow bad? or any other...
2
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16 years ago
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IDE to Flash memory
Hi, I'm looking for some ideas to make an IDE to NAND or NOR flash memory interface. Have you ever heard about something about this (ip, project, chip...) ? Thanks. Franck.
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16 years ago
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FFT for an arbitrary number of points (not power of 2)
Hi, I'd like to ask experts here about ideas to perform a FFT on an arbitrary number of points (for real data). The cores usually found for an FPGA implementation only permit FFTs on a number of...
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16 years ago
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Free & open source USB STAPL Player
Hi All, I have just released a free & open source USB STAPL Player - a small device which may control multiple JTAG chains (up to 8, but only 2 implemented in current hardware) playing the STAPL (JAM)...
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16 years ago
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