Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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did i miss edk 9.2
hi just i quick question: did i miss edk 9.2? there are some service packs for edk 9.2 on the xilinx web site but i can't find edk 9.2 itself on the webpage... it still says edk 9.1. i'm i missing...
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16 years ago
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[Linker script : EDK6.3 -> EDK 8.2] Parse error
Dear I used to EDK 6.3 for multiprocessor system implementation. The system worked fine. But, when I upgraded to EDK 8.2, "parse error" occurs in the following linker script....
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16 years ago
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FPGA Clock signal
i would like to ask how can i capture the FPGA master clock signal in the oscilloscope? Bcos in the data sheet, it indicates that the master clock is located at pin N9 which is not accessible...
5
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16 years ago
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Time Delay in FPGA
hi, i have two processes in my vhdl code for my FPGA. the two processes each will generate a signal with the second one lagging around 5ns. problem is, i am told that this 5ns delay might not be from...
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16 years ago
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Why dynamic partial reconfiguration is still not there?
Many researchers are very enthusiastic about dynamic partial reconfiguration. Benefits are great. Theoretical basics are discussed since relatively long time, but we still don't have any widely...
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16 years ago
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ERROR:MDT - transparent bus interface connector
Hello all, I am facing the error below when i am doing generate libs and BSB's. ERROR:MDT - transparent bus interface connector 'xxx_bram' is only referenced once! any views? I am using XPS 6.2...
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16 years ago
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May i program a Spartan 3 fpga with a 1,8 V Digilent cable?
Hi ,i like to use cpld and fpgas scraped by boards at home at the purpose of practicing VHDL. I have some Spartan 3 XC3S1500,and an inexpensive Digilent JTAG cable rated 1.8 to 5.5 V. There is some...
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16 years ago
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not totally repulsive
I usually have +5 volts available in VME modules, so I generally linear-regulate down from +5 to 3.3, 2.5, and 1.2 for Spartan3 fpga's. VME has lots of power and lots of air flow. My favorite trick is...
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16 years ago
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Linux capable free/GPL SOFT CPU for XC3S500E?
Hi All, I'm looking for a possibility to run Linux (may be a ucLinux) on a XC3S500E containing CPU and some custom peripherials. The hardware platform should be a Spartan3E Starter Kit (rev. D), or...
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16 years ago
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FPGA I/O Selection in UCF
I have an application with a Xilinx Spartan3 FPGA where I would like to use a single FPGA binary to support to I/O voltage levels: 2.8v and 1.8v. My question is as follows: Why does the UCF file...
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16 years ago
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linking error using mb-g++
Specification EDK version:8.2i FPGA Board: Virtex II Pro My source code requires g++ compiler. However, when trying to use g++ to compile a very simple code on EDK 8.2i, the following error appears....
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16 years ago
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Global Variables
i am having two PROCESS to take advantage of dual-edge behavior of the clock pulse. one process takes care of the rising edge while the other process takes care of the falling edge. For the two...
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16 years ago
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Linux (not uClinux) on Microblaze 7.0 w/MMU?
Now that Xilinx has released Microblaze 7.0 with an optional MMU (in EDK 9.2), has anyone started working on a Linux port? There's already a uClinux port to Microblaze with no MMU, but for some...
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16 years ago
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Audio Output from Spartan 3 Starter Kit
Hello, I would like to try to get some audio output from my Spartan 3 starter kit board, but as a hardware novice I worry about damaging my board. Is there any risk of damage if I connect a...
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16 years ago
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DDR2 Interface
Hi I am designing a board with a Virex 4 and a DDR2 component. I have use the MIG tool to generate an interface. However the pinout it has generte is not ideal as there are a lot of crossed nets. Can...
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16 years ago
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