Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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synthesizing vqm with parameters with quartus 7.1sp1
Hi, I have a verilog module in my project, which is instantiated in the design 3 times, each time with different parameters. I generated 3 different vqm files outside the Quartus project (with...
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16 years ago
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Altera webpack for Linux?
I noticed that the Xilinx webpack version of ISE now runs in Linux. I seem to recall in the past that the webpack was a Windows only tool, so this seems like a signficant shift. Does anyone know if...
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16 years ago
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Quartus II warning: "pass-through logic has been added"
I tried asking this in the Altera forum, but to no avail. The crux of my question is why the template that Quatus itself suggests results in a warning and how to fix that? For portability and...
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16 years ago
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Coolrunner in system programming - XAPP0058 - viable?
I looked at XAPP0058 which describes some algorithms for in system programming of some Xilinx CPLDs. It appears that there are enough data to program a XPLA3 device once I have the binary data I want...
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16 years ago
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how to KEEP_HIERARCHY [EDK]
dear In EDK 8.2, I am finding how to set up XST synthesis option "KEEP_HIERARCHY = YES", with no luck. Could someone tell me how to set "hierarchy" for synthesis step? Thank you in advance
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16 years ago
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gate count calculation in xilinx.
Hi, can anybody help in providing a document or any site relating gate count calculation in xilinx. Thanks & regards subbu
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16 years ago
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New Laptop for work
I am looking at a low end Dell laptop, the Vostro 1500, as a new computer for work. I may supplement this later with a new desktop unit for crunching FPGA designs, but I will also be using this laptop...
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16 years ago
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VHDL language is out of date! Why? I will explain.
Just look at its syntax. It is so archaic that anyone who had any deal with Python will just laugh. Try, say, to create a simple VGA controller, which is simply readable. VHDL's Ada syntax is also...
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16 years ago
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simulating xilinx block ram with modelsim
hi ich have a problem with a project in ise and modelsim. i used the core generator to create a single port block memory and instantiated it in my design. now i want to do a behavioral simulation to...
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16 years ago
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TI DSP soft core in Xilinx?
I have a V4FX based product and I'd like to have a DSP coprocessor to go with the the powerpc that handles my operating system. Are there TI c54x or c3x soft cores out there that could be compiled...
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16 years ago
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Lattice Semi
Has anyone worked with the Lattice Semiconductor ECP2M series of FPGA? Were the parts easy to get? Also, how is the ispLever design software from Lattice? I've worked exclusively with Xilinx FPGAs and...
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16 years ago
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V4FX: Cannot access EMAC1 of Dual MAC system
I am implementing an PowerPC embedded system in EDK and am trying to use both emac0 and emac1 hard cores of the fpga. I have implemented two instances of the plb_temac ip core and the hard_temac core...
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16 years ago
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EDK 9.1 Issues
When working with custom peripherals in EDK, is there a better way to make sure changes to the hardware design take effect than trying to re-import the peripheral? I spent several hours last night...
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16 years ago
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Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals for data capture and triggering?
Hi, This is an embarrassing question to be asking - how does one attach signals from the edk design to the chipscope ILA? When I sit down at my desk to debug with a benchtop logic analyser, the first...
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16 years ago
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Block-ram FIFO in Xilinx
Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Generator. In the creator I used the 36 bit data bus. Is it possible to...
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16 years ago
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