Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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An error occured while using Dual Port Block Memory
Hi! I am using Dual Port Block Memory in Virtex-II, V8.2. During simulation in Modelsim, i have encountered an error that reports to me is: $recovery(posedge clk B: .... ps, posedge clk A &&&...
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16 years ago
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FPGA Editor (9.2.03i) under Linux x86_64
I am not able to run the fpga_editor (64-bit ISE install) under my Fedora 7, x86_64 system. After I set the DISPLAY variable to :0 (instead of my :0.0 or :0.1) and trying to start it, I get following...
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16 years ago
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Why doesnt XST RAM for this VHDL description
Hi, I am using a Xilinx Virtex2 Board and would like to have an instruction and data RAM. I was following the guidelines in the XST 7.1 but there still must be something wrong with my description. At...
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16 years ago
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Xilinx Virtex 5 ISERDES vs ISERDES_NODELAY: which is better for DDR?
The Virtex 5 Library has two design elements for the ISERDES. The ISERDES_NODELAY obviously does not include the delay element, but it has another difference. It has a secondary clock input (CLKB)...
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16 years ago
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Virtex5 Evaluation Board
Hi We are thinking of buying a Xilinx Virtex5 evaluation board. At the moment this one seems to be our favorite: Price is 1195$, which is quite reasonable. Are there perhaps other good products with a...
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16 years ago
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EDK 9.2 and virtex 2 devices
Hi all, i'm currently trying to make an virtex2 project with edk 9.2i. Unfortunately all virtex2 based boards are removed from the bsb dialog (also boards with older spartan devices). Also the...
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16 years ago
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problem with adding custom logic to an IP core (xilinx edk)
Hi all, I'm experiencing problems with adding custom logic to an IP core that I have generate in EDK. I changed the vhdl file of an auto- generated IP core that is connected via FSL to the FPGA, but...
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16 years ago
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33+ Regs in PLB IPIF
I have created a custom peripheral in EDK 9.1/ISE 9.1 that needs to have 100 registers and communicates with the PowerPC CPU via the PLB bus. The board I'm using is the XUP Virtex-IIPro dev. board. I...
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16 years ago
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Parallel to Serial ASI ...
Hi, I have two simple questions : - To implement a conversion Paralle to Serial ASI (paralel data TS from Digital Tuner) you must use an FPGA or exist an chip that can make the conversion ? - If do...
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16 years ago
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TPS75003 Spartan-3(E) Regulator Design
Dear All, The TPS75003 is a triple voltage regulator designed for the Spartan-3 & Spartan-3E series. It's got some quite specific component requirements. Unfortunately, the datasheets and appnotes...
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16 years ago
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Microblaze books
hello all, I am looking for some books for microblaze and some examples with assembly for microblaze. since now i havent found anything helpful. thank you regards
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16 years ago
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Update to Xilinx ISE 9.2
Hi Sorry, for putting this question here but I have heard that the Xilinx support is quite busy so perhaps someone can help me out here a little bit quicker ;). I am just wondering if there is an easy...
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16 years ago
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mb-g++ linker script problem 8.2i
Specification EDK version:8.2i FPGA Board: Virtex II Pro I've tried generating a linker script to map the input object files (.text, .rodata, .sdata2, .data , .sdata, .sbss, .bss ) on to RAM...
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16 years ago
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GTKWave 3.1.1 for win32
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.1 which supports reload now.
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16 years ago
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Xilinx WebPack 9.2i: Download not possible, wrong links
Hello, because download was not possible I checked after some tries (as always hecticness) the links - the links are not valid! Webinstall: File Download: Of course you must first log-in. Then use...
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16 years ago
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