Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How to simulate these example CORDIC code?
Hi, I want to learn the implementation of CORDIC. I find the following website has some code which I would like begin with it. But I cannot simply simulate it in my Modelsim PE (student version)...
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16 years ago
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can't read/load memory contents
Hello there, one of new members around here. I've got a problem while i try to retrieve/pass over some values to memory. I use EDK 9.1 and a system of microblaze, opb bus and opb bram memory. I try to...
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16 years ago
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xilinx spartan 3 + 16 adc
Hi I'd like to ask if that device will process data from 16 ADC (20 bit, 44,1kHz) to one output stream (does it depend on ADC clock - i mean adc input clock = amount of output samples/s ? ) ? Or maybe...
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16 years ago
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Registrations open for VLSI Conference 2008 in Hyderabad, India
The '21st International Conference on VLSI Design and the 7th International Conference on Embedded Systems' are being held jointly from 4th to 8th January 2008 in Hyderabad, India. Please visit...
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16 years ago
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Virtex 5 PCB Designers Guide: required capacitors
Hi all, I've some trouble designing a virtex 5 board. I use the "Xilinx Virtex 5 LX development kit" schematic ( provided by Avnet ) as model, and the Xilinx App Note "Virtex 5 PCB User guide 203". My...
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16 years ago
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React on falling edge in testbench
Hi, is it possible to make an input react on a falling edge of an output in a vhdl testbench? i'm using modelsim se 6 and the following statement doesnt work: ... wait on (Ack'event and Ack = '0'); i...
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16 years ago
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converter
hi fnds, is there any software that converts 'c' program to a 'vhdl' program??
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16 years ago
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PCI Mezzanine Card with Xilinx Virtex-II
Hi I would like to use the following evaluation board to run my implementation: My intention was to use Chipscope in combination with JTAG to download the bitstream to the FPGA and then use Chipscope...
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16 years ago
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DDR2 dqs pin // virtex4
Hi, I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11" The board is equiped with a DDR2 SDRAM memorie. FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1], DQSN[0:1]. I...
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16 years ago
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DCM with instable clock
In a design, I have to generate several clocks with precisely phase relationship, I'd like to use DCM. But the clock_input is not stable. It could possiblely change frequency, even stop for a while. I...
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16 years ago
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Unable to scan device chain
I'm soldering up my first FPGA design and I'm getting discouraged. I'm using an Altera Cycline with an EPCS1 serial configuration device. I've soldered up the passives and the power supply but the...
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16 years ago
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EDK + Modelsim simulation : Memory allocation failure
Dear When I simulate one EDK project (with multi-processors), Modelsim reports an error "Memory allocation failure". I tested the EDK project with 6 microblazes and it was okay. Now I am trying to...
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16 years ago
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Measuring setup and hold time in Lab
Hi all, How can we measure setup and hold time of a flip-flop on FPGA in lab ? Regards, Ved
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16 years ago
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Xilinx XST 8.2, Error on multi-source, bug?
Hi, I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in Unit ..." It's a wire in a submodule and i checked the code: The signal is an output to module A and an input to module B....
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16 years ago
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partial dynamic reconfiguration on Virtex-4 SX35
Hi, I have just begin my PhD on SDR and I will have to use a FPGA with partial dynamic reconfiguration. The system which interest me have a Xilinx Virtex-4 SX35 integrated on it and I'm not sure this...
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16 years ago
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