Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Global Reset using Global Buffer
Hello Group I=B4ve read a lot about resets and I=B4ve decided that for my designs, an asynchronous solution with a synchronous source is a better solution. No discussions here, this is a personal...
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16 years ago
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yet another Altera Cyclone II EP2C35 dev. board
I've made another Cyclone II development board: english user manual : user manual : german project page with high-resolution photos: If you like this board, you can buy it via ebay for 179.- Euro....
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16 years ago
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Xilinx XChecker cable supported until which version?
Hi I have Xilinx ISE 7.1 and wanted to use the Xilinx XChecker cable to connect to the JTAG interface. Unfortuantely this does not work when I use autoconnect. When I try to manually configure the...
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16 years ago
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how to generate a linker script?
Hello all, i am trying to find how to generate a linker script in edk 6.2 ver. I googled it but i dint find something helpfull so far. regards, xenix
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16 years ago
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Bidirectional open drain port
Dear all, I guess Bidirectional open drain port can be implemented in FPGA...From the data sheet i understood that it can be either at logic low or High impedance. My question is how Bidirectional...
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16 years ago
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scanf and printf in EDK's BSP
I am working on a PPC405 system using EDK9.2 and its BSP. The system uses an uartlite as stdin and stdout. I am unable to have scanf and printf functions to work as they should with strings. Per...
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16 years ago
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Spare Spartan3's
Hi, I've got some spare Spartan3-200's (XC3S200TQ144) which are left over from a project. I have ~40 non-RoHS compliant parts & 50 that are RoHS compliant. Let me know if you're interested Dave
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16 years ago
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ISE and Itanium
Hi everybody! Is Itanium supported by ISE software? Best Regards
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16 years ago
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Hook open drain "power good" to nSTATUS or nCONFIG?
I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open drain "power good" signal and a cap to delay that after startup. It looks like I could hook this to either nSTATUS or nCONFIG to...
4
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16 years ago
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Converting a ByteBlasterMV into a ByteBlaster II?
Argh. I just discovered that my ByteBlaster MV clone can't program an EPCS configuration PROM, but the ByteBlaster II can. Google led me to a web forum that suggests an MV can be converted to a II,...
3
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16 years ago
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Xilinx Dual processor design
Hi all I am using Xilinx dual processor reference design suite to develop dual processor (xapp996) system on virtex-2 pro. I want to port an operating system on to this design Is it possible to port...
3
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16 years ago
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Start-up Xilkernel on Microblaze
Hi, How many long Xilkernel take to startup with microblaze (System Clock : 50 MHz). On my design, the Microblaze need more than 30 second to create the first thread after xil_kernel_main(). Regards,...
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16 years ago
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using fpga as programmable connection
hi, i would like to use a small fpga (or cpld) on a pcb to make direct bidirectional connections between pins. basically it should act like a programmable "cable". is this kind of application possible...
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16 years ago
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Fifo Block-RAM Xilinx ISE - port empty
Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Generator. In the creator I used version without registered outputs (1 clock...
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16 years ago
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vhdl state machine
I have a following state machine. enable is an input comiing from a accumulate core. Now the total number of inputs to be accumulated varies but is always greater than 5.so the maximum frequency of...
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16 years ago
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