Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Using SRAM Memory CY7C1386C
Hello, I use SRAM Memory CY7C1386C. I downloaded datasheet and vhdl model from I read that " Available speed grades are 250, 225, 200 and 167 MHz" Does it mean that ONLY these frequences are...
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Configuration via JTAG using an Embedded Controller
Hi, I am usign the Xilinx xapp058 design to program another device on the JTAG chain. In this design I download a xsvf file over a serial link and once it's done, the processor will play the xsvf to...
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Traffic Light with counter
hey guys i hope u can help me out... i want to design a simple traffic light controller according to the 4 states shown in the code below. my only problem is that my signal state_reg is not changing...
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Christmas and New Year at Enterpoint
Guys and Girls We are going to have an extended Christmas and New Year shutdown at Enterpoint this year. Last date for us to ship a board is 21st December 2007 and restarting 7th January 2008....
 
ise timing analysis + different clock domains
hi since i'm pretty new ise i have a couple questions regarding timing: currently i'm working on a design for an spi interface. so far everything is ok but now i need to work with 2 clock domains....
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Using DDR RAM on XUP V2Pro board
Hello, I'd like to ask if there's a way to get the DDR RAM on the XUP V2Pro board by Digilent up and running without using the PLB DDR controller? I know here are a few designs for V2Pro, but I'm not...
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Pipelining of FPGA code
Hi, I am trying to understand what Pipelined designing/architecture for FPGA's mean ? I went through documents which list all the benefits of using pipelining for FPGA's. But, none of them explicitly...
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EDK 9.2 Woes
I updated to EDK 9.2 primarily b/c we are building a new project and I wanted the latest MPMC3 core. Here are some things that I have noticed while using it: 1) Instance name changes in the EDK GUI do...
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EDK IPIF development workflow
I am new to EDK (but not ISE) and have some questions about the workflow for developing a custom IPIF peripheral. The documentation implies that the peripheral is re-imported into EDK once it's...
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Hand solder that FPGA on your prototype
Hi all, I've just finished constructing a new site that has web videos of soldering techniques, including how to hand solder quad flat packs. Very handy for prototyping. You can go and get a free...
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Drawing timing-diagrams for documentation
Hi *, just stumbled across this opensource-thingy and thought it might be useful to others as well: I've been looking for something just like this... cu, Sean
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Asynchronous FIFO and almost empty - bug?
Hi, we are using an asynchronous FIFO to bridge two clock domains. Both domains have "the same" clock speed but different clock oscillators. We shift data phits in the FIFO which always form a data...
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Cascaded DCMs with variable phase shift (Xilinx)
Hi all, I'm using a Spartan-3 XC3S400 with cascaded DCMs. 1st DCM is configured as variable phase shift with 27MHz clock from an external VCXO in CLKIN. It is fedback (1X) from CLK0 through an IOB...
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Interfacing Cyclone III to 3.3v LVDS devices
How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks
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ISE WARNING Xst:647
Hi, I have a design that works fine in Quartus. In the process of porting it to ISE, I'm getting a series of these warnings and can't for the life of me work out why... An example: WARNING:Xst:647 -...
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