Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Can't get Quartus to Infer Dual Port Ram for Stratix2GX
How do I get Quartus to infer a dual port RAM? I've tried a couple of coding styles neither worked. I've also tried putting a /* syn_ramstyle = "M4K" */ on the module statement and on the ram...
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16 years ago
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UK FPGA supplier
Try in Oxford.
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16 years ago
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XILINX XABEL
Hi, Is there anyone that has XABEL for Sun available, due to some internal mess we have managed to loose our old XABEL installation. It was used with XACT 5.2.1 and Viewlogic powerview which we still...
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16 years ago
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EDK does not find Modelsim
Hi, I want to launch Modelsim from within Xilinx EDK. I have the correct versions installed, the ISE recognizes Modelsim correctly. EDK says it cannot find Modelsim, although i have set the following...
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16 years ago
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calculation of clock cycle /instructions...
Hai all, Is there any formula to calculate processor clock cycles per Instructions with given parameters as FPGA implemented processor clock frequency and instruction bytes... pls suggest.. regards,...
2
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16 years ago
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Xilinx Platform USB Cable
Hi I have a very basic question. I have got a Xilinx Virtex-II board with an JTAG interface. I was thinking of using the Xilinx Platform Cable to communicate over the JTAG Platform Cable USB attaches...
2
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16 years ago
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Power PC ISOCM Simulation
I am simulating a system where I use the ISOCM and DSOCM for all code manipulation/data movement to/from the PowerPC. I have verified that the system_init.v file is poulated and pointing the...
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16 years ago
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Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?
To avoid going to a larger package, I want to mix LVDS_25 inputs with LVCMOS33 in the same I/O bank, with VCCO = 3.3V. I would also like to use the DIFF_TERM attribute on the LVDS inputs, to avoid...
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16 years ago
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Xilinx ISE Bugs
Hi all I have read here that quite some people are encoutering problems with the Xilinx ISE tools. So for example the XST like to remove signals from the datapath although they are required. I recall...
3
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16 years ago
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Re: lossless compression in hardware: what to do in case of uncompressibility?
Op Thu, 29 Nov 2007 15:42:45 +0100 schreef Denkedran Joe : Given that uncompressible data often resembles noise, you have to ask yourself: what would be lost? If you can identify the estimated...
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16 years ago
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Researching Reconfigurable Computing
I've been looking into reconfigurable computing as a research topic for my final year project in Computer Science. I've pretty much settled on this topic but am struggling to figure out what exactly...
2
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16 years ago
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Memec Flancter app note?
The Flancter circuit is described in an article by Rob Weinstein of Memec in Xilinx Xcell Journal issue 37 page 54. The PDF of the entire issue is on Xilinx' FTP server: ftp:// The article makes...
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16 years ago
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XHwICAP functions on EDK
Dear all, I am now trying to use XHwICAP_getClbBits() (and also setClbBits()) to change contents of LUTs on EDK. But they do not work well. My fpga board is XUP (Virtex2 Pro.) I write a part of...
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16 years ago
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can't genarate block memory cores in ISE 7.1i
Hi I had to use version 7.1 because 9.2 looks too heavy for my old pc I tried to generate internal block memory,but i have the following message Customizing IP An error occurred during customization...
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16 years ago
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What option can change the path sign "\" in Quartus ?
Hi, I find a strange problem relating to Quartus 7.2 and Modelsim 6.1g, web edition. For functional simulation, all is OK. For timing simulation, the component cannot be recognized by the testbench...
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16 years ago
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