Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Trouble with instantiation of RPM core - RLOCs are not obeyed
Hello, I have successfully made an RPM core using the floorplanner "Write RPM to UCF" feature and created a and a core.ucf file. Before I created the core I applied the AREA_GROUP constraint to get a...
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16 years ago
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Different synthesis report between ISE-xst and EDK-xst
Hi all! I've really trouble to implement a simple application on a XUP Virtex- II Board using the PPC and PLB as Interface. I simply want to pass two inputs into the logic-core wire them to two output...
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16 years ago
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Registrations open for VLSI Conference 2008 in Hyderabad, India
The '21st International Conference on VLSI Design and the 7th International Conference on Embedded Systems' are being held jointly from 4th to 8th January 2008 in Hyderabad, India. Please visit...
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16 years ago
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PCI Parallel port card for JTAG / programming?
Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and programmers for micros (AVRs), CPLDs (Xilinx/Altera/Lattice) and FPGAs...
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16 years ago
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GAL16V8
Hello, I have a simple project in mind and have some GAL16V8 PLD's knocking around, could anyone suggest a design suite that still supports these devices along with an associated url. Many Thanks....
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16 years ago
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Xilinx ise 9.2i clean up project files
Just recently an error/bug arises in ISE when i go to synthesise a design. The synthesis will just error without any transcript text. when i cleanup the project files and then run XST it synthesises...
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16 years ago
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ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date
Hi I just tried to initialise the JTAG Scan when I get the following error: Info: impact:501 - 1 Added Device done ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date Please check your...
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16 years ago
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keep_hierarchy attribute equivalent for Lattice/Synplicity?
I was wondering if anyone could help me figure out one thing that is holding us up for porting some Verilog code that works for Xilinx/ISE to Lattice/Synplicity. Specifically, for Xilinx, we use...
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16 years ago
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Questions about Timing closure Floorplan and individual timing constraints
Hi everyone: Is there any manual about the symbols in Timing closure Floorplan, Quartu II? I do not find a detailed description about that. Especially, I don't clearly understand the clock control...
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16 years ago
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Net hierarchy with Xilinx 9.1
Hi, I ran into a small problem while trying to use a UCF file created for ISE 8.2 within EDK 9.1. I had a few INSTs and NETs relatively deep within the design's hierarchy: INST...
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16 years ago
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Xilinx EDK simulation
Hi, I've been able to run a simulation of a PPC405 system example with ModelsimPE if the executable elf file fits into block ram, but I can't find a good example of running a program out of external...
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16 years ago
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What to look for when synthesising verilog code originally written for ASIC to FPGA?
Regarding to necessary changes to verilog code, am I missing something, 1. caches and memories, replacing using FPGA block rams. 2. clock gating to clock enable 3. change latches to registers Anything...
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16 years ago
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Drigmorn1 More Info
Some more information on our new low cost Spartan-3E development board Drigmorn1. First FAQ and reference design material now on our engineering website. Links to FAQ and application/reference pages...
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16 years ago
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DDS generator with interpolated samples for Spartan3E development board
I've read the Wikipedia article about Direct Digital Synthesis ( ) and building a DDS generator with a FPGA, which interpolates between adjacent entries in the lookup table, looks like some fun. This...
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16 years ago
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problem interfacing AD9510 via serial controller
Hi all, I'm trying to implement an analoge capturing project using Xilinx sx55 fpga and AD9510 as ADC. But I'v difficulty to program AD9510 clock distribution IC via its serial controller port to set...
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16 years ago
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