Field-Programmable Gate Arrays - Page 132

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• 06-20-2006
• Quartus 6.0 Fitter Critical Warning
• • Manfred Balik
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• 5

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• 06-20-2006
• JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
• • Fred
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• 6

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• 06-20-2006
• Microblaze, -mxl-gp-opt and small data areas
• • Zara
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• 0

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• 06-20-2006
• Programmable clock ics8442
• • subint
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• 0

• 
• 06-19-2006
• Processor Design
• • Hans Rhein
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• 1

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• 06-19-2006
• Virtex-4FX embeded MAC and Rocket-IO data corruption??
• • Marc Kelly
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• 9

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• 06-19-2006
• Xilinx bitgen vs output file name
• • johnp
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• 1

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• 06-19-2006
• Aurora core example simulation
• • Catherine Trammell
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• 1

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• 06-19-2006
• using Impulse-C free edition for VHDL only FPGA designs.
• • Antti
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• 5

• 
• 06-19-2006
• xst:What happened here?
• • Morten Leikvoll
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• 2

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• 06-19-2006
• ABEL to VHDL translate
• • Steven P
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• 2

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• 06-19-2006
• Utility to generate pin assignments (UCF, QSF) from the Protel netlist
• • Wojtek Zabolotny
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• 0

• 
• 06-18-2006
• Newbie to FPGA
• • anand
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• 12

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• 06-18-2006
• pad issue
• • kelvins
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• 0

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• 06-17-2006
• Temperature sensing diode on Vertex 4
• • Vassili Savinov
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• 2

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• 06-16-2006
• High speed differential to single ended   [ 2 ]
• • vans
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• 34

• 
• 06-16-2006
• Floppy to FPGA?
• • fslearner
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• 16

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• 06-16-2006
• Doubts on IBUFGDP
• • vssumesh
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• 1

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• 06-16-2006
• Hold margin for asynchronous Interface
• • pinku
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• 1

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• 06-16-2006
• bga routing
• • Marco
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• 10

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• 06-16-2006
• library for lmb
• • savs
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• 0

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• 06-16-2006
• Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with...
• • james7uw
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• 1

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• 06-16-2006
• anybody doing self-timed/asynchronous on post-jbits xilinx parts?
• • Adam Megacz
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• 1

• 
• 06-15-2006
• How process statement works in vhdl
• • ZHI
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• 2

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• 06-15-2006
• Virtex2-Pro local clocking...
• • johnp
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• 4

• 
• 06-15-2006
• Anyone get a Pictiva OLED to work?
• • Bluespace Technologies
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• 12

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• 06-15-2006
• Bug in Altera Quartus
• • lecroy7200
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• 0

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• 06-15-2006
• Virtex-4 with Rocket IO capability??
• • Vivek Menon
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• 5

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• 06-15-2006
• ARM cores in FPGA ?
• • sjulhes
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• 11

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• 06-15-2006
• private army of jun g. lockett
• • unsaman
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• 0

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• 06-15-2006
• XPLA3 bidirectional bus
• • Maroc
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• 1

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• 06-15-2006
• open inputs and Unisim libraries
• • Brian Davis
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• 0

• 
• 06-14-2006
• LVTTL or LVCMOS for PCI Signaling?
• • kia rui
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• 6

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• 06-14-2006
• Xilinx XST Error
• • Alex McHale
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• 4

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• 06-14-2006
• boot mode pins on Spartan3
• • Marco
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• 6

• 
• 06-14-2006
• ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
• • Vivek Menon
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• 9

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• 06-14-2006
• ARM9 DDR interface
• • subint
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• 0

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• 06-14-2006
• null waveform element and webpack
• • nomalus
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• 2

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• 06-13-2006
• Quartus 6.0 and VCS
• • Michael Laajanen
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• 0

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• 06-13-2006
• Does anyone have documentation for an insight DS-V2LC board
• • nylander
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• 0

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• 06-13-2006
• S3E Starter Kit webcast
• • John_H
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• 11

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• 06-13-2006
• ANNC: VHDL Coding for FPGA Webcast
• • bart
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• 1

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• 06-13-2006
• IDELAY clock spec. in Xilinx V4
• • Symon
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• 6

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• 06-13-2006
• Virtex-4 FX12: Mini module board from avnet
• • Vivek Menon
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• 0

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• 06-13-2006
• FSM state minimization with ISE?
• • backhus
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• 15

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• 06-13-2006
• Can i use "burstcount" in my userlogic while using Altera SOPC builder 5.1?
• • xuweijun1983
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• 0

• 
• 06-12-2006
• Looking for patent attorney specialized in programmable logic
• • HT Chang
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• 4

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• 06-12-2006
• Virtex4 DCM in DRP mode
• • Guru
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• 3

• 
• 06-12-2006
• How to get lowest price for a ModelSim license?   [ 2 ]
• • Weng Tianxiang
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• 25

• 
• 06-12-2006
• RocketIO AC coupling
• • Roger
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• 1