Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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System Generator Design examples for spartan3, virtex 2pro?
Can someone please point to a site where we can get some good design examples for Sysgen (not the ones mentioned in the guide) ? Thanks in advance.
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16 years ago
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Getting started guide for Digilent Spartan 3E Starter Board?
Hi there - I recently got a Digilent Spartan 3E Starter Board ().It's been a while since I played with an FPGA, so I was hoping to find a really comprehensive guide that would walk me through...
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16 years ago
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Spartan-3E starter kit, what's "J8" 6-pin for?
What's the 6-pin connection "J8" on the lower-left of the Xilinx/ Digilent "Spartan-3E starter kit" (rev D) wired too ..?, can't find it in the schematics.. Google search doesn't turn up anything...
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16 years ago
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Using LVDS_25 with 3.3V Vcco.
What voltage swing will and common voltage will a LVDS_25 configured port output when the Vcco is 3.3V and not 2.5V as the datasheet specify ..? Will it damage the FPGA or anything else ..?
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16 years ago
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serial ATA question
This is probably a long shot but I'm wondering if serial ATA can be run at a speed less than 1.5 Gbps? I have a V4 fpga but no MGTs so it would be nice if I could make it work with regular chipsync...
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16 years ago
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Connecting BRAM block to Self designed BRAM controller
Hi all, I am using XPS 8.2i and ISE 8.2i and a virtex-4 a part of assignment, I have to write a verilog/vhdl code for a BRAM controller by which we can perform read/write operation on a BRAM block.I...
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16 years ago
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Chrontel 7010A
Does anybody have experience with Chrontel 7010A (CH7010A)? I input BT.656 digital video to Chrontel 7010A. I'm trying to get DVI output. For now, my only concern is the DVI mode of operation (not TV...
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16 years ago
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using fstream to access File on Compact Flash Card
Specification EDK version:8.2i FPGA Board: Virtex II Pro Compiler : mb-g++ I'm tring to create a file stream using ifstream instr("") or ifstream instr("a:\") to create a file stream from CF card. In...
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16 years ago
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xilinx v5 configeration problem
When i use chipscope 9.2 to configerate bit file, sometimes will occour warning like this "WARNING - Device 0: ICON Core version v15.15 is not supported", and the configeration failed. When this...
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16 years ago
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Spartan 3E starter kit expansion boards - Gb ethernet & video
I have been thinking about doing 1 or 2 expansion boards for the Spartan 3E starter board to add Gb ethernet & camera capability. Has anyone done this already & is willing to sell a copy ? Save me...
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16 years ago
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`ifdef XST?
Does anybody know if XST defines any testable variables when compiling verilog code? Some of the compilers or simulators that I'm using have differing $readmemh() semantics, and I'd like to be able to...
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16 years ago
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Darnaw1 User Manual
First cut of the Darnaw1 user manual is now available here John Adair Enterpoint Ltd. - Home of Darnaw1. The PGA FPGA solution.
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16 years ago
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ML505 board Compact Flash
HI everyone, I have purchased ML505 virtex5 based kit for PCIe testing. It has one pre-loaded compact flash with some in-built testing environment. My uses is PCIe testing which this compact flash...
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16 years ago
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How do you initialize Xilinx ISOCM memory using DCR interface
I'm trying to use the Xilinx ISOCM memory in a Virtex-II Pro. I can't seem to get it to actually write to the ISOCM BRAMs. In .mhs file I have: BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER...
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16 years ago
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WARNING:PAR:289 and bitgen error.
Hello, I'm having problems with XIlinx ISE 9.1. My design works fine on behavioral simulation but when I want to implement i, I get an error in bitgen stage. I get a warning message in PAR stage:...
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16 years ago
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