Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx Evaluation boad ISE sample project
Hello ! Does someone have verilog-HDL sample apply to Xilinx Evaluation boad [TB-4V-FX60-PRO] ? I want to sample source. I will implement only ISE tool by nothing EDK tool.
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16 years ago
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Xilinx DCM outputs for DDR
Greetings, What's the best way to clock DDR flops from a DCM? In all the DDR I/O I've produced, I've always used the DCM clock output through a BUFG, feeding the normal and inverted versions of that...
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16 years ago
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multidimensional arrays in VHDL?
I am trying to covert the following Verilog code to VHDL. I am having issues with converting the arrays to VHDL. Could you please comment on how this should be done module FIFO16x8(DataOut, DataIn,...
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16 years ago
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Tarfessock1 - FPGA Cardbus Development Board
Images of the new version of Tarfessock1 here We have replaced the connector that has been giving us supply issues and we expect to complete testing of the new version in early January. They will ship...
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16 years ago
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How to use a generic memory with Xilinx ?
Hello all I am struggling with ISE and CoreGen to generate a memory block that would be customizable (mainly in depth & width) through generic parameters. The Memory block generator datasheet seems to...
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16 years ago
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Debugging EDK DDR interface
Hi all, We built a custom board with Spartan3 1200E and Quimonda 32MBx16 DDR (HYB25DC512160CF-6). The schematic is similar to Spartan3E StarterKit. Now I am trying to put the DDR to life in EDK using...
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16 years ago
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global clock (gclk) input at xilinx virtex4 fpga
Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the device or if it's advisable to use more than one due to the...
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16 years ago
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Xilinx MAC experience ?
Hi all, We are going to start a project in which we will need to use the hardware MAC Ethernet module in a Virtex 5 for high speed transferrs (around 400KB/s) through 1000BT. I'm looking for...
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16 years ago
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sampling error between 2 clocks
Xilinx V4SX35 ISE 8.2.03 Modelsim I got CLKI(300MHz), CLKI_DIV(150MHz) generated through a counter(just a flip_flop) clocked by CLKI, both clocks connect to BUFG. Then I use CLKI to sample data...
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16 years ago
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Generating a RPM in Xilinx floorplanner
Hi, I have some trouble when I try to generate a RPM using the floorplanner tool in Xilinx. I'm trying to make a RPM from a quite large design but cannot get it to work. Now I'm trying with a...
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16 years ago
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[help]SAS with FPGAs
Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do IC design before ,so this project is very difficult for...
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16 years ago
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What timing constraint value should be set for input/output module?
Hi, There are several modules in a design, which will be assigned to several member in the group. If the system clock is 100MHz, what timing constraint value should be for each input Pad-to-Setup and...
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16 years ago
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Mico32 linux kernel git repository
Hi guys, finally Mico32 linux kernel source tree is available as a git repos. Anyone interested in joining the journey could get it from: git clone git:// test-lm32 cd test-lm32 git checkout -b...
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16 years ago
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Why the core dynamic power isn't 0 when the toggle rate is 0?
This may sound like a stupid question to you. But I really don't understand how come the core dynamic power is still quite large when toggle rate is. In my understanding, there is no signal change...
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16 years ago
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LVDS on Drigmorn1
In answer to all of you who asked about LVDS support on Drigmorn1 we believe 2 pairs of LVDS are very viable but as yet have not tested the feature. Some others may be possible but pin routing is not...
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16 years ago
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