Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
help with rising edge matching
Hello, I'm trying to write VHDL code that detects when two signals both rise fro zero to one at the same time. Do you guys have any idea on how to do this FPGAguy
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Routing Vccint on four-layer PCB
I'm not very experienced at SMT PCB layout, but I'm trying to design a four-layer board with an XC3S50A-4TQG144. I'm using inner layers for 3.3V (Vcco, Vccaux) and GND. Am I asking for trouble if I...
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What is "4-state binary radix" in Modelsim
Hi, For Modelsim XE 6.1e, it says the following on page CR-27 of command reference. I do not understand what is the "4-state binary radix". Could you tell me what it means? Thanks a lot. Searching for...
 
ASIC verification job info request
I am looking for a reality check. I have 10 years experience doing software verification on EDA tools, in particular hardware emulators, System Verilog, and VHDL. When looking at some job ads I see...
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Quartus and simulation libraries...
Hi all, I used to work with Xilinx ISE, there you could compile the unisim, simprim libraries. I have switched from Xilinx to Altera where I would like to with the same ease compile Altera specific...
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Xilinx EDK PPC405+FSL
hi i'm using edk 9.1 and i have to write my own ip core. i want to use the ppc405 in a virtex 4 an was wondering if that supports the fsl link. in the datasheet for the fsl link it only talks about...
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Emacs as GUI for NIOS-II
Which makefile should I use and where should the current working directory be located if I want to run a NIOS-II software build from the command line or emacs (linux or cygwin) rather than using...
 
Xilinx's ML505
Hello group, Anybody know if DAC plugin modules exist for the Xilinx ML505/ML506 board ? Thanks, John
 
FPGA program cable suggestion
Has any a good suggestion for a fpga program cable, which is known to work with linux (64 bits)? Thanks T.
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Changes to use lwip 1.2.0 with Xilinx EDK 9.1 or earlier
Below and at are the changes to use lwip 1.2.0 with Xilinx EDK 9.1 or earlier It seems the lwip api has changed slightly. I don't have EDK 9.2 so I don't know what version of lwip is included, but EDK...
 
Glitch warnings in Modelsim with Lattice ispLever 7.0
Hi all, I'm having trouble trying to figure out why this VHDL synthesizes to something which generates glitches when post-route simulated in Modelsim. Regardless of what I do, I always get tons of...
 
BGA reflow soldering using vapor phase
I am doing some initial research regarding PCB design process with a Spartan3E (FT256) .. Have i understood it correctly that avnet are the only distributor of xilinx FPGA=B4s ? .. in that case, i can...
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Altera USB-Blaster on RHEL 5?
Has anyone worked out a hack to get the USB-Blaster to work with Red Hat 5? I need to put DE1 project boards in a lab with linux boxes that have already been upgraded to RHEL 5. If anyone has figured...
 
Virtex BRAM Configuration
Hi Folks, I am totally new to FPGA design, so excuse me if this doesn't make sense. Is it possible to configure the 18K Bram in Virtex II in a different way. For example as four different 512 deep...
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MGT Transciever
Hi alll, I am trying to setup simple TX and RX communication using the MGT Transceiver without any 8b/10b encoding. I see the exact output TXP and TXP pins. But the RX data decoded seemed to be...
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