Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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question on AND
I have 2 inputs x : unsigned bw : integer when x>bw I want to check if x(x'length downto bw) = "1111111......" How do i write this in VHDL since my length of x is unknown at this point. Normally if x...
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16 years ago
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XPS MPMC
Hi all , I have been stumped by xilinx tools again ! I have just baught a Evaluation board , whos supporting software , base system etc where writen using EDK 8.1 using older IP cores. Now I am using...
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16 years ago
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Vendors of FPGA's
If I am looking for buying just the FPGA chip itself - not a development board - where could I buy this? What do commercial buyers do? Best Regards Hansen
4
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16 years ago
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What does this do ?
Hi, Can anyone tell me what this bit of code is doing ? -- declarations ------------------------------------------------------------------------------------------- signal phase : std_logic_vector(6...
2
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16 years ago
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simulation problems
I havw writtent the following code. It compiles correctly. When i run the simulation it just stops and points to this statement variable result : unsigned(bw-1 downto 0); The code and test bench are...
5
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16 years ago
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Ethernet on recent FPGAs
Hi, Am far from being an expert in fpga usage and programming, I was wondering if there exists any ip cores out there that would allow the use of ethernet interfaces on recent FPGAs. For instance say...
24
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16 years ago
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Differential output drive-strength in spartan-3
I am instantiating an LVPECL iobuffer in a xilinx spartan-3 device. This buffer is sending out data at 150Mbps into an LVPECL receiver chip located about 18 inches away. The sent signal doesn't have...
6
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16 years ago
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Area group constraint
Hi, I have a question regarding area group constraints for Xilinx ISE software Using VHDL to describe this: I have an entity A that uses 3 components B, C and D as well as glue logic connecting...
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16 years ago
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Camera connection on XUPV2P
Hello, I've some issues hooking up some external components (camera link base cameras) to my XUPV2P board. I've built a PCB which connects the hig speed expansion port of the XUPV2P to the outputs of...
12
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16 years ago
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12 | |
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WebPack on GNU/Linux
Hi all ! I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with iverilog and testbench associated. Waveforms with gtkwave looks good. I have been trying to synthetise a simple 8bit...
16
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16 years ago
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round,fix and floor algortihms
I would like to know which round,fix and floor algorithm would be best to be implemented on an FPGA. I am working on a DSP project. I want to write funtions in VHDL which can be called and would...
13
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16 years ago
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Xilinx, How to generate PAD file, from the UCF file
Hi, I am working on a Xilinx Virtex5 design. I generated a pin lock file (ucf) and have a top level verilog file. Top level verilog file does not have any code, but it has only IO I want to generate...
3
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16 years ago
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OpenCores tracker and forum doesn't work?
Hi All, I just tried to submit a bug to OpenCores, and found that even though the report input form works (eg. ) the image required to fill the "key" field is not displayed. If i right-click the image...
1
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16 years ago
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Looking for used spartan3 fpga board
Hi All, I am looking for an old Spartan3a fpga board to test a school project for my sister. If you have and want to sell , please contact me. Regards Thuy
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16 years ago
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spartan 3e JTAG programming
Hi guys I have two spartan 3e's and a coolrunner in a single JTAG chain. If I program either FPGA from power up its outputs do not drive, but I can read the JTAG user register and it has the value...
1
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16 years ago
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