Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FPGA's as DSP's
I have heard that FPGA's can have a much larger throughput, dollar per dollar, than a special purpose DSP chip because of their parallelism. Anyone here have any experience or pointers on this topic?
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16 years ago
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Help! Micriblase + plbv46_pci in Virtex5
I am connect plbv46_pci(in slavemode) to Micriblase. =F7ut in Plase&Route ISE give warning: WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router...
3
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16 years ago
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fpga pin to pin conecting
Hi everyone Can someone please help me. If I have to connect two FPGA circuits on the same board and their pins are not compatible waht should I do? If someone knows some good link about this,...
5
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16 years ago
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5 | |
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sine and cosine wave generation
Can anyone give guidelines on how to generate sine and cosine wave in VHDL?
9
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16 years ago
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Debbuging a RISC processor on an FPGA
Hi I have implemented a RISC architecure and RTL simulation in Modelsim works fine. So the next step would be to run this architecture on an FPGA and see if it still outputs the correct results. So...
13
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16 years ago
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Where has Xilnet gone?
Hi all , I am new to xilinx tool and currently I am working with a project constructed using EDK 7.1. I am using EDK 9.2. In this old project Xilnet is used for a webserver demo talking to an external...
5
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16 years ago
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5 | |
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Read/Write SRAM on Spartan3 Starter kit
Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am trying to test the SRAM on the S3 starter kit board with the following code: if ToWrite then...
3
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16 years ago
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libusb-driver and Spartan3-AN Eval kit woes
Hi ! I appologize if that has been dealt with already, though I haven't found an answer in the archives. I have an x86_64 machine running some recent linux (ubuntu hardy dev. amd64), Xilinx ISE...
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16 years ago
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Virtex4 burn-in failure
Hello, I've observed a failure of one of our Virtex4-based products that is a bit puzzling. The device had been in operation for several weeks before failing, and is among a run of a couple hundred....
10
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16 years ago
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10 | |
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Final call for papers
Final call for papers The 2008 MULTICONF (website: ) will be held during July 7-10 2008 in Orlando, FL, USA. We invite draft paper submissions and the deadline for paper submission is very close. The...
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16 years ago
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BRAM Readback
Hi all, Is there a simple way to read back data from Virtex5 BRAMs preferable over JTAG by XSFV/SVF commands? Best regards Ed
2
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16 years ago
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Spartan 3AN LVDS I/O
I have a working Spartan 3E design that I am porting to XC3S200AN. It has a handful of instantiated ODDR2s connected to instantiated OBUFDSes, such as the following: serchan_gen : for chan in 0 to 3...
4
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16 years ago
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opb_emc_v1_10_b
Hi all , Is there any place where I can download opb emc 1.10.b as my lates EDK istallation doesnt have it? BR Rate
4
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16 years ago
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4 | |
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Timing constraints not applied, ISE & SynplifyPro
Hi, I'm a new synplify pro user. This tool seems to be much powerfull than XST for apply timing constraints. But there is something I don't understand : in the synplify pro report, I can see all my...
2
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16 years ago
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Resource utilization broken down by hierarchy?
Hello, I am interested in looking at the resource utilization of a design I am working on broken down based on the RTL hierarchy of the design. I am using a Virtex-II Pro part. I have seen in the past...
4
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16 years ago
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