Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Grisoft AVG false positve virus detection in Xilinx software.
Guys, I saw this and thought of you... Syms.
7
|
16 years ago
|
7 | |
|
|
Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?
Has anyone succesfully used Aldec Active HDL 7.3 (web-eval) with a (Verilog) Smartmodel simulation? I'm using Xilinx Webpack 9.2i.04 (IP-Update#2), and I separately downloaded and installed the Aldec...
2
|
16 years ago
|
2 | |
|
|
regarding DMA memory to memory copy in NIOS II
here is my codes. I want to verify the result and display at the end, however I got like "cdcd", what's wrong? thanks /* * "Hello World" example. * * This example prints 'Hello from Nios II' to the...
4
|
16 years ago
|
4 | |
|
|
Power Supply Bypassing Presentation
Hi - Power supply bypassing being a hot topic in these parts, some folks may be interested in the following. According to the IEEE Santa Clara Valley IEEE EMC web site, Steve Weir of Terraspeed...
—
|
16 years ago
|
— | |
|
|
My first Flash FPGA
Hi all, I started a book witht that titled in 2006, but never finished, as I found the sources now, well it is still unfinished, but maybe it brings some smiles onto the faces of some FPGA developers,...
9
|
16 years ago
|
9 | |
|
|
equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix II GX-90
i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II GX-90 in terms of the resources available in these devices (logic, block ram, dcms,...
3
|
16 years ago
|
3 | |
|
|
Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's Systemverilog support was quite far behind Modelsim 6.2g. Now, I was wondering...
16
|
16 years ago
|
16 | |
|
|
Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)
Hi *, since switching to ISE9.2, one of my favourite topics has come up again... Basically, what I have is an FPGA with a bank that has a VCCO of 3.3V. This bank has several LVTTL outputs and a few...
2
|
16 years ago
|
2 | |
|
|
FA: Brand New Altera MasterBlaster up on Ebay
No reserve.
—
|
16 years ago
|
— | |
|
|
Synplicy and Xilinx - no PAR
I've got major issues here. I've installed Xilinx 9.2i with the latest updates and service packs, and am trying to get Synplify 8.9 to actually work with it. The problem is that although I can compile...
3
|
16 years ago
|
3 | |
|
|
Xilinx Spartan 3A/DSP with Coregen 9.2i?
I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.) When I ran Core Generator 9.2i.04 (with IP Update #2), created a new Spartan3A/DSP project, then looked at what wonderous...
—
|
16 years ago
|
— | |
|
|
buying fpga kits in denmark
Hi , Can anybody give me some information on buying fpga kits in denmark? ..iam interested in the altera cyclone 3 starter kit! .,guess its possible to order from Altera directly , but i might have to...
3
|
16 years ago
|
3 | |
|
|
Thoughts about memory controller problems
Hi, I tried to boot Linux on my FPGA-prototyped SoC system. The Linux image is running from SDRAM which is controlled by a Dynamic Memory Controller, but the Linux boot always stop at somewhere...
2
|
16 years ago
|
2 | |
|
|
Endpoint Block Plus v1.5 example design
Hello, I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core with ise's coregen and compiled the smartmodel libs also with with ise. But when...
1
|
16 years ago
|
1 | |
|
|
OV7660 CMOS camera
Hi all, Am working with this camera. wanted to know if anyone else has worked with it before. I have a set of register settings and want to know if that is right. i am working towards getting a RGB...
—
|
16 years ago
|
— |