Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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new to NIOS II
Hello group, Recently I have started to learn NIOS. I will appreciate it if somebody knows any good online resource or book that I can use. Thanks, Amit
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16 years ago
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About 10-bit pixel datum from CMOS image sensor
Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am using a Spartan3 starter board to interface with a Micron CMOS Image sensor (MT9T001), and is...
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16 years ago
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Xilinx prom programming problem
I have a custom board with a V4 LX60 and a XCF32P config prom. I can config the FPGA directly via JTAG, but I cannot program the prom. I hope someone can point out the stupid mistake I'm making. I am...
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16 years ago
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PC requirements for ISE webpack
I am thinking of buying (or upgrading) my PC for an FPGA project. At the moment I am using a windows laptop for synthesis and P&R runs. I use a Linux PC for simulation runs. Ideally I would like to...
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16 years ago
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ROM/LUT
I'm trying to understand the intricacies of implementing a ROM in an FPGA. I've searched around and come up with some useful tidbits, but I was hoping someone here could clear up a few issues with...
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16 years ago
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EPC in Xilinx EDK 9.2
I use External Peripheral Controller to access various peripherals from my MicroBlaze/PPC based systems. To allow access to slow serial off-chip peripherals I always set C_PRHx_RDY_WIDTH long enough...
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16 years ago
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Regarding Hyperterminal
Hi, I have a quick question, and its been bothering me for at least 3 hours. So I made a project in EDK, and I simply want to run the memory test (powerpc). When I followed all the steps (generate...
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16 years ago
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question on record types
I have defined two functions as below function complexMult (a_i,a_q,b_i,b_q: signed) return complex is variable a,b : complex; variable result : complex; begin assert a_i = a_q report "Error :...
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16 years ago
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difference between net skew in the clock report and clock skew in trce log
Hi all, I've something strange in my design... I think there is something I don't understand.. I've a clock distributed on a global clock network, It seems to be ok.. In the "Clock report" from the...
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16 years ago
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Xilinx PAR problem when using chipscope
Hi I have design that will PAR fine when chipscope is not included but whe it is I get the following error :- The placement constraints of the IOBs app_rd_n and app_AD[7] makes thi design unroutable...
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16 years ago
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Can I connect PLB and OPB to mlcroblase v7 (use EDK 9.2 and Virtex 5) ?
in MHS : #********************************************************* BEGIN microblaze PARAMETER HW_VER = 7.00.b PARAMETER INSTANCE = microblaze_0 PARAMETER C_INTERCONNECT = 1 PARAMETER C_DEBUG_ENABLED...
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16 years ago
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define a new bust interface
hi all I want to work with xillinx edk and add an ethernet core to my design. I used hard-temac core and to connect this core to plb bus I must use plb-temac. but this core consume alot of slice. I...
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16 years ago
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BPSK CORDIC tracking
Hi all, I would like to know how we can demodulate a BPSK signal with CORDIC algorithm. How can we (with CORDIC) make the phase acquisition and tracking due to an IQ conversion without a Costas...
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16 years ago
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Spartan3 I/O question
I have a Spartan3 Bank VCCO pins connected to 1.8V. Normally I use this bank to generate 1.8V push-pull signals but I needto drive out 3.3V signal on this bank. Can I drive out open drain output with...
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16 years ago
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HDLC
Can anyone point me to a sight with HDLC schematic or drawings? Thanks
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16 years ago
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