Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Virtex5 not for SONET or SDH
Hey guys, Be careful when using Virtex5 for SONET. The RocketIO tile only has 1 PLL used for transmit and receive on both bidirectional ports. This PLL is normally sync'd to the local reference so the...
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16 years ago
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Partial Reconfiguration of Virtex-5: ISE and EAPR?
Hi all, Does anyone know whether Virtex-5 devices are supported by the Partial Reconfiguration design flow. I understand that PlanAhead supports it but which versions of the ISE and the EAPR support...
7
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16 years ago
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7 | |
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Single Top FPGA Tips
Hi all, I thought I would share this report that I just wrote called "Single Top FPGA Tips". It's a bit different to your normal "Top Ten Tips" or "Favourite Recipes" because I tried to write a single...
8
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16 years ago
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8 | |
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Simple Memory Read problem, help appreciated
Hi I have a strange bug in my simulation and cant figure out the error. I have a simple ram that contains data that should be read as described in the following process: PROC_ram : process (clk) begin...
11
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16 years ago
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11 | |
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Simulator error 607
Hi everyone, I'm running Webpack ISE 9.2i (just updated to 9.2.04i/J40) on Suse10.1. This is not the 'blessed' RedHat but so far, this has worked great for compiling simple VHDL and putting it on a...
1
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16 years ago
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1-Wire and Dallas DS1WM in Spartan
Hi! I have implemented the Dallas/Maxim 1-Wire master DS1WM (version v1.100) in a Spartan3A. It works fine most of the times, but in some implementations it just won't work. Changing something silly...
2
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16 years ago
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OPB timer Microblaze
Hello all. below is a part of my code for an OPB timer attached to a Microblaze with no inerrupts. the timer counts correct but when reaches the value 0xFFFFFFFF ( end point) should roll over and...
2
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16 years ago
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Problems with GDB in EDK 9.2
I posted this on the Xilinx EDK forum without success so far. I recently upgraded to EDK 9.2.02i and built up the TestApp_Peripheral executable for the Xilinx Spartan-3E Starter Board Rev D. I can run...
2
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16 years ago
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2 | |
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ML505 with Petalinux
Has anyone successfully ported Petalinux in Microblaze (ML505) and used the SATA AHCI driver? Is the AHCI driver from Petalinux distribution working OK?
2
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16 years ago
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2 | |
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simulator options
Hello, I am looking for a basic simulator which can help me with testing functionalities of my VHDL and Verilog designs. I am running Windows Vista. What would my options be? I am an entry level...
1
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16 years ago
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Modelsim Warning
I am getting the following warning in Modelsim # ** Warning: Design size of 10053 statements or 1 leaf instances exceeds ModelSim PE Student Edition recommended capacity. # Expect performance to be...
5
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16 years ago
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Sythesisable subset of VHDL
Hi I have done some VHDL implementations that were successfully running on an FPGA. However, I still feel unsecure about what constructs so that the design is working in the end. I am using XST, they...
2
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16 years ago
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2 | |
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New leonardo spectrum version has license errors
Hey everyone, Just wonderting if anyone else has upgraded Leonardo Spectrum in a while. I went from a (very) old version 2003b_65 to 2007a_37 and now I'm getting erros when it tries to load libraries...
1
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16 years ago
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1 | |
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GCLK overmapped
Hello, From searching, I see that others have had this same problem, but the solutions were vague and old (2002). I'm using XPS 8.1 with Spartan IIE 600 and I'm trying to bring a couple of signals...
1
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16 years ago
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1 | |
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How to optimize my design area to fit?
Hi all, I am currently building a Digital Down Converter on Xilinx System Generator 9.1 platform which unfortunately overshot resources provided by mt target Virtex 4 chip by 400%. Is there any...
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16 years ago
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