Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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When are FPGAs the right choice?
I've been programming embedded micros for a long time, and have a decent understanding of hardware. I finally ordered an FPGA development kit (still in the mail) because I find the whole FPGA concept...
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16 years ago
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setup time not met in Quartus
Hi all, I have a source clock 125MHz (ck125), and it has a derived clock 25MHz(ck25). I find that Quartus generates ck25 by the clock tree of ck125. To a register A (regA), ck125 has a clock arrival...
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16 years ago
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floating point arithmetic in vhdl
Hi, is there a library for that , or do I have to code it myself ? Would you be interested in s.th. like that ? Regards Thorsten
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16 years ago
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mb-g++ compilation error with EDK 8.2.02i
Specification EDK version:8.2.02i FPGA Board: Virtex II Pro I just upgraded EDK 8.2i to 8.2.02i. In 8.2i compilation of my source code using mb-g++ works. Compilation however, failed when upgraded to...
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16 years ago
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Spartan 3A starter kit
Hi, Does any one know any examples on the xilinx web site or in the CD (which is sent with the starter kit) that can be downloaded to development board. If someone can help me on this, it would be...
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16 years ago
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Newbie looking for guidance
Good Afternoon- I posted this to comp.dsp the other day but had someone suggest I post it here. I'm interested in learning more about DSP's and actually getting my feet wet with DSP hardware. I have...
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16 years ago
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Redundant Ethernet connection
Hi all, This is somewhat OT, but I am not sure where to ask... In a V4FX based system I need to come up with a way of having 2 ethernet connections to a backplane. The original plan was to use two...
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16 years ago
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Virtex4FX over-voltage
On a Virtex4FX, if the Vccint was run at 2.5V instead of 1.2v, what problems would someone expect? And after what period of time? For example, if it was over-voltage for 2 minutes, the GT's would be...
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16 years ago
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Does PC-FPGA communication requires a driver?
Hello, I want to design FPGA-based PC oscilloscope controlled by a user of the PC. I am not sure how to provide communication between PC based application (a main program on PC; this will be written...
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16 years ago
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'1' or '0' when I/O pin is pulled up
Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am trying to write and read registers from a CMOS sensor via I2C. The SCLK and SDATA pins are...
3
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16 years ago
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Vitrex5 JTAG capture and debug
Hi, I'm currently implementing a design with a fairly large amount of static configuration data. It would be good to be able to capture the values of the registers in the FPGA and verify that they are...
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16 years ago
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Partial reconfiguration reference design?
Dear I heard that there is a good "partial reconfiguration" reference design : Reconfigurable Audio Filter Demo. I am searching in xilinx site with no luck. If someone knows where I can find, please...
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16 years ago
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Reed solomon IP core
Hi all, Looking at the Xilinx IP core documentation I found only 2 versions of reed solomon decoder implemented on Virtex-5 (RS decoder version 6.1) and Virtex-2pro (RS decoder version 5.1). I need to...
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16 years ago
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how to implement this...
Hi lets assume I have two signals, each carrying 8 bits of information. One signal is a so called configuration signal and has exactly 4 bits that are HIGH and 4 bits that are LOW. Now depending on on...
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16 years ago
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Xilinx ISE and XP home,possible?
Is it possible to install the last version of the free ISE on XP home edition?let me know,please Thanks to you all Diego
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16 years ago
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