Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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CAN Sniffer on Altera DE2-115 Board
Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation boar d with the Terrasic AD/DA data conversion card (High Speed Mezzanine Card ( HSMC) via SMA. I am using two A/D...
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5 years ago
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CPLD 1.8V to 3.3V bidirectional SDA
I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and fsync. Vo ltage level on the sensor board is 1.8V the PI is...
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5 years ago
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Sharing VHDL Verification IP
Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community h as previously been difficult because there was no standardised way of inter facing to and controlling these VVCs. A solution...
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5 years ago
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verilog reg usage
Does
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5 years ago
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Xilinx Custom IP accessing 16-bit bram
Hello, I have used Xilinx core generator to synthesize a bram with width of 16 bit and depth of 80k, resulting a 17-bit address. Let's call them bram_data, and bram_addr. I am connecting the bram to...
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5 years ago
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Free Webinar Thursday: UVVM ? The standardized o pen source VHDL testbench architecture
The webinars are hosted by Aldec as follows: Thursday 26 April: EU: 3:00 PM ? 4:00 PM (CEST) : 12 US: 11:00 AM ? 12:00 PM (PDT): 11 ----------- For an FPGA design we all know that the architecture ?...
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5 years ago
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engineered data path versus inferred data path
Seem to get better results when using inferred data paths? E.g. letting the synthesis tools insert the multiplexers where they see fit gives better Fmax than laying out the datapath in complete...
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5 years ago
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FPGA selection recommendation
I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like to connect it to a 16-bit DRAM, so there should exist a...
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6 years ago
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Altera Cyclone V SoC availability...
I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx...
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6 years ago
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the FPGA one-shot
I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various pin locations and speed/drive strength settings. Most of...
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6 years ago
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How to handle a data packet while calculating CRC.
Hi, I'm trying to process a Ethernet type package. Suppose if i have detected S FD and now have a
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6 years ago
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Lattice or Microsemi?
What are thoughts on these two vendors goods? I like that they have cheap(er) PCIe options. My intended use case is to learn about HW and HDL development with an existing strong OS development...
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6 years ago
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Microsemi now Microchip
In case anybody missed it: Hans
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6 years ago
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Is Zynq7000 leaky?
Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is "On-chip boot ROM", but is it mask-programmed or flash? If there are flash cells, then what other...
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6 years ago
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Most power efficient FPGA?
Hi, I have been away from in-depth FPGA development for maybe a decade! I am looking to design an embedded camera product where power use is key. I'd like to use an FPGA for some video manipulation...
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6 years ago
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