Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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set_input_delay min and max (timequest)
Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a databus...
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16 years ago
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Typical jitter of high frequency oscillators?
I'm looking for a "rule of thumb" of what I should expect in terms of jitter on the clock signal. It should be relatively easy to find what jitter an oscillator has (e.g. one datasheet said 31ps...
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16 years ago
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Using ICAP in s3a to reconfigure
Hi everybody, I am currently working on the mulitboot feature of xilinx s3a. I have programmed one of the on-board PROMs with 3 different files at different locations but there are lots of issues...
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16 years ago
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Hardware Cosim no output
Hi all, I am doing hardware Cosimulation in System Generator via JTAG PLatform USB cable to my ML501 Evaluation kit but my Cosim block does not have any output. I have already configured the cable...
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16 years ago
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Does Altera has some analogous file like XDL of Xilinx?
Hi: Does anyone know whether Altera has some analogous file like XDL of Xilinx so that we can read the place and route of the circuit of Altera's FPGA textually? If not, I wonder whether there is a...
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16 years ago
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Synthesis of functions in Quartus
Hello all, I have a bunch of functions I would like to synthesize on Quartus. These are going to be part of a library. I would like to get resource utilization of each function. The functions are...
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16 years ago
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sFPDP IP Core
hi, I am quite a newbie with FPGAs and would like some opinion about existing sFPDP IP Cores for serial communications. We are considering the use of a Virtex-5 ML506 Development Board with GTP...
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16 years ago
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Xilinx parallel cable 4 clone
Hi, I just purchased Enterpoint's Darnaw1 module. I have Xilinx parallel 3 cable not Parallel 4 cable. Is it possible to configure spartan3e with Parallel cable 3 through the parallel cable 4 header?...
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16 years ago
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About John Williams' ICAP driver?
Hi everybody, I have successfully integrated the ICAP driver to our Linux on the PPC on the ML310 board. But now I had a problem about the ICAP driver. My combinational circuits, such as the very...
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16 years ago
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Picoblaze enhencement and assembler
Hi, I wasn't very satisfied with the available assembler, so a few month ago I wrote a new compiler for the Picobaze during my spare weekends ... I just though I'd share it if anyone is interested...
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16 years ago
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Seed Values
I would like to know how the initialisation of seed values would affect the output of the procedure of UNIFORM. I have looked at UNIFORM but I am not able to understand the significance of the seed...
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16 years ago
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The Java processor JOP is now GPL
Hi all, it has been silent about JOP in this group for a while. However, development is still very active. I've now decided to put the project under GPL v3. For those who don't know the project: JOP...
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16 years ago
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Command to unzip hardware cosim files
Hi all. I have recently downloaded the driver files in order to do hardware cosim on a ML501 Evaluation kit but I do not know how to unzip n install it to Sysgen I have heard it is a certain command...
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16 years ago
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XEM3010
Hi, i am configurating the PLL of my FPGA board to achieve a higher frequency. The master clock frequency of it is at 100 MHz. I am trying to divide it to attain 800 MHz. May i know is this possible,...
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16 years ago
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more microblaze firmware blues. tool chain version problem?
Hi all, I am currently working on porting some code on microblaze from a spartan 3 FPGA to a virtex 2 pro FPGA for expansion reasons. The code which really works on a spartan 3 FPGA, just somehow does...
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16 years ago
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