Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Re: Blast from the past
You might want to also crosspost to
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16 years ago
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AES Bitstream Encryption in Virtex-4. How safe it is?
Hi, I need to place my FPGA designs in a safe platform, and I have some questions: 1. Does anybody know whether Virtex-4 AES bitstream protection has been broken? 2. Do you consider it a good...
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16 years ago
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[Altera] How to infer some code into ROM-blocks (in automatic way), but not all
Hi. My qustion is probably dumb. But i'm stuck here. In my design I have a lot of code that can be inferred into ROM automatically, and it does. However, my device doesn't have enough ROM blocks. My...
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16 years ago
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FPGA for a DVB common interface implementation
Hi, anybody has any (practical) information about the Common Interface specification for DVB receivers? I have some ideas (for example a DVB-CI module that feed the transport stream from DVB receiver...
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16 years ago
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PARAMETER C_SPLIT error
Hi, I'm working with the EDK 9.2 MicroBlaze Tutorial and get the following error message: ERROR:MDT - D: line 245 - PARAMETER C_SPLIT has value 8 which does not fall in the range (1:C_SIZE_IN-1),...
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16 years ago
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reconfiguration of virtex 2 pro
Hi friends Can u please help me in reconfiguring virtex 2 pro board... Pls give an example and steps to reconfigure virtex 2 pro.. I am using Xilinx 8.2 i version software.. If u have some codes...
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16 years ago
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verifying UNIFORM using matlab
I have written a process to generate random numbers using UNIFORM. I was trying to check the results using "rand" in matlab. How do i initialise the seed values of both these functions to the same...
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16 years ago
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"Use Multi-level Logic Optimization" -- Advanced Fitting option
At the beginning of February, DJ Delorie proudly posted a bin2seven project. Since my entire reason to purchase a Spartan 3e development board was to experiment, I decided to take DJ Delorie's project...
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16 years ago
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my Spartan-4 wishlist
here it is: 1) devices densities like in Spartan-3 (50..5000) 2) devices packages like Spartan-3E (including QN132 !) or better (microBGA 6x6 mm?) 3) all good features of S3A/AN !! 4) design security...
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16 years ago
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ICAP for readback on Microblaze...
Hi everybody, I'm trying to partially reconfigure my device (XC2VP30 on ML310 board) through ICAP. I have my ICAP attached to OPB which is attached to Microblaze. In bitgen.ut file I have set the...
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16 years ago
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clock distribution accross boards
Hi, maybe you folks can help me with a design decision: I need to distribute a clock to up to ten identical boards. The boards are all plugged into a backplane in a single row. In addition to the...
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16 years ago
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Virtex-5 FXT coming soon?
Hi, the fact that forum posting about ML507 was removed by Xilinx moderator (from Xiliinx forums), gives us at least the information that ML507 is a Virtex-5FXT development board. This should mean...
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16 years ago
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FPGA/CPLD group on LinkedIn
FPGA/CPLD group on LinkedIn Group for People Involved In the Design and Verification of FPGA's and CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD Design/Verification on your...
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16 years ago
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Synplify crashing
I am using the Lattice ispLever tool for their PLDs and I seem to be having trouble with Synplify. It crashes frequently and I don't see any particular reason for it. It doesn't correspond to any...
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16 years ago
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clock generation
hi i have a basic doubt in fpga implementation. i am new to this. i have made a stepper motor controller and implenting it on a DE1 board. i have no problem in simulation. everything is working fine....
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16 years ago
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