Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Need Help regarding I2C Protocol testbench
Hello folks, I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state machine. The problem with simulation result is that it is...
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5 years ago
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Need Advice regarding Interfacing of Max9850 audio DAC with spartan 6 FPGA
Hello Folks, I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C Interfacing. I'm Using VHDL Language For coding. Does Someone worked on this before? or worked related to this....
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5 years ago
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System Verilog Import package error
Hello, I have a few packages that I have written like this: package A;
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5 years ago
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What to do with an improved algorithm?
Hi, I think I've got a really good way to improve a commonly used & well establ ished algorithm that is often used in FPGAs, and it all checks out. The imp lementation completes the same tasks in...
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5 years ago
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Re: Cheaptest FPGA board for Computer Architecture
[snip] The boards I have bought are shipped 5000km for free, and one at a time do not attract customs charges. The Icestorm tool chain is open source, so could be adapted for layout control,...
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5 years ago
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PipelineC
Hi folks, I have a little project I've been working on to make a better HDL-like language. It's a subset of C so should be familiar. I am using a Digilent Arty Artix-35T board and have a working UDP...
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5 years ago
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We are looking for invited speakers for our conferences and seminars: 5th Reconfigurable Market
We are looking for invited speakers for our conferences and seminars. Our main interest will be talks about reconfigurable market (FPGA). But we are having problems getting their names and contact...
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5 years ago
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8 bits vs. 9 bits in RAM Blocks
The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. Does this...
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5 years ago
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Stepper motor controller
Hello all, I used Hamsterwork's stepper motor controller , there position out for leds etc. How i can make give position back.. I.E. I want to give position to stepper motor controller not push a...
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5 years ago
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How to analyes IBERT ip results for highspeed signals?
Hi, I just started working with IBERT ip from xilinx. Can anyone suggest some references to look into to analyse the ip results and how to adjust the proper 2d eye scan? Thank-You in advance.
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5 years ago
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How to chnge this VHDL code into Verilog code
architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0); --...
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5 years ago
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SPL2019 - Call For Papers
========================= ========================= ========== CALL FOR PAPERS IEEE - X Southern Conference on Programmable Logic (SPL2019) April 10th to 12th, 2019 Borges Cultural Center, Buenos...
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5 years ago
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Searching for info about very old FPGA devices
Hello. My name is Rodrigo and I am from Argentina. I was looking for very o ld datasheets without success :-( (I searched a lot in google, alldatasheets, and more places...). I obtained name from old...
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5 years ago
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Communication between HDL simulation and user software via ZMQ
I develop systems were the FPGA-based hardware will use message-based commu nication (via Ethernet, USB or another communication channel) with remote s oftware. Those systems require thorough testing...
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5 years ago
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Re: Very low pin count FPGA
Xilinx has the XC95xxXL series of CPLDs, starting at 44 pins quad flat pack with leads. Very easy to hand solder. These have an internal architecture based on the old PLD devices, ie. 36-wide and...
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5 years ago
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