Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Detecting a pulse with minimum width
I have an input signal that is required to be high for a certain length in time before a halt request is issued to a processor. To detect this signal, three solutions popped into my head. 1- A shift...
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16 years ago
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Help on Virtex-II Pro global clocks.
Hi, I'm adding new logic to an existing IP. This IP uses a DCM to manage it's sys_clk. My logic is using another (external) clock which is an input port to the top level. My logic works fine if I...
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16 years ago
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I need help! Connecting my dual port RAM to a microblaze
Hi there, i have some problems while integrating a special dual port RAM core (generated in xillinx ISE) into a Xillinx EDK project. The ports of my DP-RAM are designed differently inorder to increase...
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16 years ago
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Xilinx S3DSP + EDK Board, too good to be true?
Hi All, I was looking at the Xilinx website today and saw the new Spartan 3 DSP EDK board. It seems like a pretty good deal, as the board by itself is 295, the usb JTAG cable is 199 and the EDK, well,...
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16 years ago
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DDR3 speed, Altera vs Xilinx
I get the impression that Altera is in the lead when it comes to speed on DDR[3] interfaces. Can anyone confirm/deny this? Altera claims to be able to clock a 64/72bit wide DDR3 at 533Mhz on the...
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16 years ago
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ICMP checksum
Does anyone know ICMP checksum calicutation by verilog HDL?
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16 years ago
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Actel PA3 with DirectC or SVF, anybody had any success?
Hi I wonder if anyone had any success using either DirectC 2.2 or SVF files to program Actel PA3 devices. All my attempts are failing so far. 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx...
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16 years ago
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Design entries for FSM
Does anyone know how can one enter FSM in Xilinx sysnthesis tool. I have a FSM in a text format called the kiss2 format. It looks something like this: file...
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16 years ago
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simulating Xilinx cores
I would like to simulate some modules in Verilog along with a FIFO generated by ISE core. I would like to know if it is possible to simuate teh Xilinx generated cores. If so, which tools do I need to...
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16 years ago
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SDC of NCF?
Hey everyone, I recently started using Mentor Graphics Precision Synthesis for fpga's after Leonardo Spectrum stopped supporting fpga's. Now Precision is outputting constraints in an sdc file...
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16 years ago
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Problem with Spartan 3 StarterKit
Hello, ich have the Spartan3 StarterKit from Digilent. When I start the programming process in impact, all LEDs on the board go red, and on the screen an progress dialog appears. When the progress is...
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16 years ago
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ALTERA SOPC : ptf-sopc files
Hi all, SOPC version 7.1 and later use a new XML file format .sopc for storing system design data instead PTF format For PTF format a "SOPC Builder PTF File" reference manual (december 2003) was...
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16 years ago
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MAXDELAY="1.0"
I generate PCI-Express PHY with GTP datawidth is selected 8bit or 16bit. but ,both the phy wrapper MAXDELAY constrain are "1.0" ! as you know,it is hard to meet the timing. I expect the 16 bit...
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16 years ago
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Almost offtopic about HDL optimizing.
Hi. I see how Quartus synthesizer removes unused parts of algorithm implemented in HDL, optimizes it and so on. Other synthesizers probably do the same. My question is almost offtopic: is there any...
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16 years ago
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Xilinx ISE Evaluation DVD 10.1 request...
Please, please, please fix the DVD installation-wizard, so that you can install the 32-bit (Webpack) tools on a 64-bit platform. (This goes for both MS Windows and Linux.) I really hate having to...
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16 years ago
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