Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
FSL or DMA w/ FIFO?
Hello everyone, My project has several ADC channels with 16bit data up to 24kSPS. There is no need for each ADC sample to be sent ASAP to the microblaze, as the data is processed in chunks of 200...
7
|
16 years ago
|
7 | |
|
|
Xilinx interview questions
Hi, I have been called for a Xilinx internship (Computer / Electrical Engineering) interview. Could any of you please let me know what kind of questions may be asked? Thanks,
4
|
16 years ago
|
4 | |
|
|
Chipscope
Hi! We are students working on implementing FFT on FPGA, virtex 4. We used Chipscope to test our code and capture signals off the hardware while its running. when we tried to test an 8 bit adder using...
5
|
16 years ago
|
5 | |
|
|
dual clock fifo
I wish to design a FIFO to tansfer data from a high speed clock domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use the cores available from any of the vendors. Inputs => DataIn //...
21
|
16 years ago
|
21 | |
|
|
EP2S130F1508C3N STRATIX II FPGA
Can anyone help me an Altera Stratix EP2S130F1508C3N? I need 500 pcs, but will take partials. Thanks in advance for taking the time to look into. Jon E. Hansen (949)864-7745
—
|
16 years ago
|
— | |
|
|
Intermittent failure to start sw app on pwr-on, SysACE reset doesn't help - must cycle pwr
I am experiencing intermittent failure on a custom V4FX20 board. The majority of the time when power is applied the SysACE configures and starts the application correctly. I have an external watchdog...
—
|
16 years ago
|
— | |
|
|
Xilinx Webcase Workflow
Austin, Peter, whoever: If someone dealing with a webcase finds that he is not the right person to deal with the case they usually suggest that I start a new case with an additional keyword to have it...
7
|
16 years ago
|
7 | |
|
|
Designing CPU
Hi. It's probably not very good place for asking such, but there're should be at least those who knows starting points. We need to design our own CPU which can be very slow. It can execute each...
20
|
16 years ago
|
20 | |
|
|
implementing ethernet FCS code in verilog
hi, i am going to use easics tool for generating crc32 verilog code (8bit input) ( . i was able to implement correctly.but i need more info to how use this crc to generate FCS of a ethernet packt. i...
3
|
16 years ago
|
3 | |
|
|
Wondering about "LatticeMico32 Open Source Licensing"
the headers of the latticemico32 verilog source files don't imply changed code may be redistributed: // This confidential and proprietary software may be used only as authorised // by a licensing...
5
|
16 years ago
|
5 | |
|
|
Xilinx impact, boldly going into nightmareland
ISE 9.2SP4 blues again.. HDL synthesis passes only after anti-virus disable, ok learned that ISE is now in VIRUS category. but how to program with Impact? until SP4 it was somewhat understandable, you...
1
|
16 years ago
|
1 | |
|
|
Need help in SDR
Good morning,my name is Emad i leave in egypt ,i taken BSC in communication & electronics engineering with GPA "A" an now i preper my master in SDR technology.but i don't have any idea to How can i...
2
|
16 years ago
|
2 | |
|
|
ISE 9.2SP4 error
ERROR:HDLParsers - Cannot reanme dependency database for library "work", file is "xst/work/". Temporary database file "C: prj pgas3askuart_bypassxstworkxil_284_5" will remain. System error message is:...
10
|
16 years ago
|
10 | |
|
|
ISSI SRAM.
Hi, I have a simple question about memory organization. I would like to write a memory controller for IS61LV25616AL SRAM (256K x 16) but I am having trouble understanding how the memory organization...
1
|
16 years ago
|
1 | |
|
|
Xilinx Tristate Registration
My tristate signals are not being placed in the IOBs. They are clocked signals, always all on or all off, depending on reading or writing, and the registration happens the fabric, not in the IOB. The...
10
|
16 years ago
|
10 |