Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Power Estimation of Microblaze (Power PC) based architectures
Hi I'm trying to estimate the power consumption of an architecture based on either Microblaze or PowerPC running a simple application (bubble sort). Using the EDK and ISE I managed to build the timing...
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PCI Express Configuration Testing
The Linux lspci -xxx command can show my PCIE device header space(0x00~0xFF). However,simultaneity,the Correctable Error and Unsupported Request error from PCIE Capabilities device status register are...
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Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
Hi everyone, Just ordered a Spartan 3A ExtremeDSP Starter Kit. It comes without a programming cable, but I figured I could re-use the cable from my trusty Digilent parallel cable from the Spartan-3...
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Configure Spartan-3E w SD-Card?
I think someone here mentioned the possibility to configure an Xilinx Spartan-3E fpga with an SD-Card (MMC) in SPI mode. However when checking on this by chance today I found that it seems to not work...
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SD-Card SDHC artificial 32GB limit
I just noticed one can get SDHC (SD-card 2.0) with 16 GB capacity for 89 EUR. The limit according to the v2.0 standard for SD-Card is 32 GB. But the layout of the configuration memory (CSD) allows...
 
Linux 2.6 PCI Device Driver on Virtex 4
I have spent the past few months slowly trying to get a PCI design with Linux 2.6 on the Virtex 4. I have been able to overcome some of the hurdles; however, I am still unable to boot up a working...
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Altera EPM7032S reading checksum
Hi, is it possible to read a checksum of a EPM7032S with Byteblaster an Max Plus II without having any information of how and what can be inside only for test the Jtag is ok? If yes how can i do?...
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DDR SDRAM interface for Virtex II Pro and Spartan3a
Hi I'd like to share with you my experience concerning DDR SDRAM interface development for XUP V2P baord, it may save your time and money. I spent long time working on it, trying to make the code...
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ISE 10.0 finally with multi-threading and SV support ?
Will the 10th edition of ISE, to be relealed next week, finally support multithreading/SMP machines to reduce synthesis + P&R time? Will we finally get support for synthesis of System Verilog...
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A Challenge for serialized processor design and implementation
Hi I have been think and part time working towards a goal to make useable and useful serialized processor. The idea is that it should be 1) VERY small when implemented in any modern FPGA (less 25% of...
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problem with edk9.2
Hi, I am trying to write values in to the slave registers through a c problem here is that i am not getting a connection between hardware and the c code ,I am not able to write into or read from the...
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Using TimeQuest Timing Analyzer
Hello, I'm trying to identify the critical path of a sequential circuit using the TimeQuest Timing Analyzer. However, I'm facing some dificulties because the tool doesn't provide, as the Classic...
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Optimizing an inferred counter
Hello everyone, After banging our heads for last few weeks (sometimes literally), I figure I'll query the group of experts here. We have a design that is functionally correct (ModelSim test bench) but...
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serval PCIE issue
1>The Power Management Capability of PCIE can be removed? Is it option or necessary? My PCIE-based GbE controller reports NMI error after ifup command. Uhhuh. NMI received for unknown reason 20 on CPU...
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vhdl type conversions
hi can anybody help me out with my problem please: i have a custom type: type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address, Generate_Strobe, Write_Data); signal state : STATE_TYPE;...
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