Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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problem with uartlite in microblaze
Hi, I 'm learning to use microblaze (microblaze, EDK 9.1 sp2). I try to use the Send function of uartlite. Please, find below my c code. the result of this code (with hyperterminal) is : -- Entering...
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16 years ago
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Sorry to Those Who Deem This to be Spam: Employment or Scholarship
Sought
Ladies (if any actually read or and gentlemen, You may have been wondering why I have not been posting much to Usenet and since September 2007. In January 2006 I became a Ph.D. student in the largest...
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16 years ago
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JavaBotics Marmaduke board
i need some detailed information about the Marmaduke board. JavaBotics website doesn't have enough information on some of the components. and i also wanted to know if the board is for sale, or not?
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16 years ago
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PCI Express Switch
Hi We are currently looking for switch solution based on PCI express to connect several Xilinx FPGA boards together. It should have compatible connector to some current FPGA Boards (e.g Using SMA or...
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16 years ago
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CAM implementation using Dual port ram
Hi, I am going through a xilinx app note. The basic CAM that is shown is a 32X9 capacity. The total memory capacity used up to implement this is 16kb. I am wondering if the idea is to generate just a...
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16 years ago
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FPGA board with an ADC
Hi, I am looking for an FPGA board with preferably a Xilinx FPGA (Spartan 3 or Virtex series) with 500k to 1 million gates capacity. The board should have any or all of the following interfaces. USB...
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16 years ago
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need help.....how do i download an image onto a virtex 4 fpga
Hey, I have to run these codes related to jpeg compression and motion estimation (dct, quantization etc.....), in order to do that i have to first upload an image into the ram of the fpga. i'm using a...
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16 years ago
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Dual Independent Aurora Links on One GTP Tile
Hi all, Hope to get some guidance here. Target device is the Virtex-5 SX50T on the ML506 eval board. I'm trying to build two independent Aurora links on one GTP tile. Independent meaning the two links...
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16 years ago
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[CORRECTED] Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
Hi, We have been using Xilinx ISE 8.1 (foundation, evaluation license) and Chipscope Pro 8.1 (evaluation license) with an ML 403 board. Both above tools could talk to the board via a PC IV cable...
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16 years ago
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Sub: Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
We have been using Xilinx ISE 8.1 (foundation, evaluation license) and Chipscope Pro 8.1 (evaluation license) with an ML 403 board. Both above tools could talk to the board via a PC IV cable without...
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16 years ago
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zpu processor core
hi, Did anybody give the new "zpu" core a try located at In a way it's an attractive core with a 32 bits processor which is at the same time very small. Yesterday I compiled the gcc tools for linux....
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16 years ago
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Xilinx ISE 9.2i out of memory
Hi, ISE reports an out of memory error while synthesizing a design which has 10,000 instantiations of a simple verilog module. The module uses Xilinx primitives FDRSE, RAM32X1S and few assign...
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16 years ago
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ddr2 controller for xilinx 1800a dsp starter kit
Hi xilinx geeks, mig2.1 can generate a ddr2 controller only for 3400adsp starter kit. is there a fully tested design suitable for the 1800adsp starter kit available somewhere ? xilinx provides only an...
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16 years ago
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Simulink(Matlab)/FPGA serial communication
Hi, I have developed a Decoder in verilog and successfully simulated it on an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an instrument control toolbox which allows one to read and...
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16 years ago
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Simulink(matlab)/FPGA serial port communication
Hi, I have developed a Decoder in verilog and successfully simulated it on an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an instrument control toolbox which allows one to read and...
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16 years ago
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