Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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NoisII or else.
Hi, Simple question. Can I put a NiosII on an FPGA alone, no ROM no DRAM no SRAM no nothing, Just the FPGA ? (examples and kits put me on the opposite extreme) I understand that I would have little...
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16 years ago
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OBUF gate delay
Hi, I am using virtex4 device for my designs. In timing analysis i found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is that a way , i can reduce this gate delay by giving some...
3
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16 years ago
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MIG/Corgen to XPS core insertion
Hello all, I am creating at MIG a external DDR2 Memory controller. Then i am trying to add this core to an XPS design. This controller i want to be attached at the PLB bus. When i am going to import...
3
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16 years ago
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Avalon Bus <-> Wishbone Bus
I'm pretty new to fpgas, but theres an i2c core on that I'd like to use in my Altera project. I understand Wishbone is a subset of Avalon, but what is involved in bridging these two together? I'm...
3
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16 years ago
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Modify POF with new ESB (ROM) content?
Hello, We have a design that has an embedded PIC processor that uses ESB's for instruction and data RAM. The target is an Altera APEX 20K100 with an EPC2 configuration PROM. What we would like to do...
9
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16 years ago
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FPGA configuration mode on ML310
Hi! everyone I have a very basic problem. I know that the 6-position DIP switch on the ML403 board can control the configuration address and FPGA configuration mode. On the ML310 board, I am not sure...
4
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16 years ago
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4 | |
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19th IEEE/IFIP Rapid System Prototyping Symposium
------------------------------------------------------------------------- Please, feel free to forward this message to interested people. We apologize if you receive this email more than once....
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16 years ago
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Xilinx xilfatfs and systemACE speed issue
Hi I am trying to squeeze some read speed out from CF using systemACE and xilinx standard libraries, but the performance is really really bad read using xilfats 400KB/s read using systemace low level...
4
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16 years ago
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system level language: why all this fuss about
why all this fuss about the need for new system level languages and higher abstraction...systems were also heterogeneous in the past but only few experts did implement them...hardware and software...
9
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16 years ago
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Use of floating point numbers in xilinx EDK .........
In my project the values are floating point. Since these floats take huge memory we have taken an SDRAM controller . These values are input to a custom peripheral which is linked to Microblaze through...
1
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16 years ago
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problem with synthesis of a state machine
The following code runs well in simulation mode but synthesis fails. Please let me know how I can get this synthesized, thanks! Fei `timescale 1ns / 1ps module blink_led(clk, d, led); input clk; input...
5
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16 years ago
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PLA datasheet - PLS161
Hi all, I am looking for the datasheet of the PLS161 which was a PLA. My interest in it is purely academic. I am teaching a high level digital electronics course and would like my students to see a...
2
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16 years ago
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Project Ideas
Hello everyone i have been working on FPGA and CPLD's for the past 6 months and i have gained sufficent expertise to do something innovative or atleast challenging in my final year project.I have...
1
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16 years ago
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Xilinx inferred FIFOs
What is the current status now about inferring FIFOs in Virtex 4 or 5 with VHDL ? Brad Smallridge Ai Vision
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16 years ago
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UK Embedded Masterclass
Hi, just a quick note to let you know that we are running another Embedded Masterclass - it is in London and but to be repeated in Bristol (8th and 13th May). For those of you that have never...
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16 years ago
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