Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Split register in smaller segments
Hi, I'm working on a little UART to get more familiar with verilog, and right now I have the following input: parameter width = 32; /* Must be multiple of 8 */ input [width - 1: 0] iData; /* number of...
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16 years ago
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Xilinx ISE synthesis error (error:3524 Unexpected end of line.)
Hello, when trying to synthesize a VHDL file (part of a design) that has already been compiled and simulated by Modelsim, ISE gives the following error: " ERROR:HDLParsers:3524 -...
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16 years ago
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Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the module with the generated xco, I am now trying to simulate the...
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16 years ago
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why to trigger a NMI error after just receiving 35 pakcets?
My PCIE device is a Gigabit NIC. The lnx ifconfig command can show the tx/rx packet count from this NIC. after loading lnx driver,it will be triggered a NMI error only if ths rx packet count reaches...
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16 years ago
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You M.ust know this to get Financial Aid!
The steps of the financial aid application process are: 1. A student applies for admission before the admission application deadline. 2. A student applies for financial aid in accordance with stated...
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16 years ago
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clock instanciation
Hi, in my book it's written that the clock has to instactiated like this : architecture Behavioral of fftest is constant T : time := 20ns; ... begin ... --clock process begin clk
4
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16 years ago
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Specifying strict setup constraint in ISE
Hi All, I need to specify the strict setup time for the group of signals. It can be relatively high, but I need very low skew between the signals. In Quartus for Altera FPGAs I can define it with the...
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16 years ago
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Xilinx FFT C-sim model
I've noticed that the Xilinx FFT bit-accurate c simulation calls are very very slow. Anyone else notice this? I am working on hybrid fixed/floating-point digital signal processing application, and I...
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16 years ago
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Xilinx CPLD programming tool under Linux
Hi all ! I'm wondering if a basic tool already exist to program Xilinx CPLD (XC95144 and so) under Linux (preferably with the old Parralle cable III) Thanks, Habib.
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16 years ago
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Task in verilog
Is task in verilog equivalent to procedure in VHDL? I am trying to convert a verilog file to vhdl. Verilog => // string data type reg [8*4:1]a; reg [8*255:0]b; VHDL => Is the above equivalent to...
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16 years ago
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looking for critique for a spartan3a lcd controller verilog module
Hello gentle readers, I started playing with FPGA and verilog about a month ago. As a fun starting project, my goal is to allow interaction between host linux pc and fpga lcd display. The connection...
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16 years ago
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Disable optimisation - Ring oscillator
Hello, I have a project where i have to implement a ring oscillator (3 not gates) using an altera DE2. But i am confronted to several problems. The voltage p-p is 128.2 mV and the Vavg is 3.308 V...
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16 years ago
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32 bit multiplier
Hi All This application I am looking at requires 17 tera bytes of multiplication per second. Which in an FPGA means 40K FPGAs. What I want to know is how many 32x32 Mults can you fit into an ASIC...
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16 years ago
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Starting a PCI Express Application
Hello, I need a PCI Express application and I could find a vendor that sells PCI Express cards and add in my design to the FPGA or I could design my own PCI Express card from the ground up. I decided...
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16 years ago
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Intel plans to tackle cosmic ray threat
Dear All, Austin in particular, I saw this and thought of you! Cheers, Syms.
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16 years ago
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