Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
"Multi-source in Unit" Verilog synthesis woes
Hi everybody, I'm working on a hobbyist board I'm designing to do some audio DSP. I'm a little new to Verilog, although not to programming in general. So far the FPGA design work has been going...
2
2
 
DOS script file to synthesize a VHDL design
Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding something from: But I still need more help. Can someone please tell me the...
3
3
 
Actel Cortex
Hey, Does anybody know if there is a port of Linux on the ARM-Cortex on Actel ? Thanks, John
1
1
 
Which to learn: Verilog vs. VHDL?
Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer by training and did some verilog in my collegiate days - but that was quite some...
44
44
 
Chipscope 9.2 in XPS
Im trying to include a chipscope core into XPS 9.2 using the Debug configuration screen. When i set up the core and try to update bitstream i get following error: ERROR:MDT - chipscope_icon_0...
 
XST support for User Defined Primitives
Hi, Does anyone know if user defined Primitives are supported with XST, I have the following code and it is giving error, primitive mymultiplexer (y, a, b, c0, c1, c2, c3); output y; // reg y; input...
2
2
 
HiTech Global Eval boards?
Hello I need a large Virtex-5 FPGA like the SX95T on a PCIe board with DDR2 memory. HiTech Global has a variety of boards with these features but I rarely here that company mentioned on this...
1
1
 
Question about Spartan 3E starter kit
Hi there - I'm very new to FPGAs and so I'm probably doing many dumb things. I recently got a Spartan 3E Starter Kit ().I followed the guide shown here: make a new project. When selectProduct...
2
2
 
Spartan3E startup problems
i got a problem with the Spartan 3E starter kit from Xilinx, no matter what Mode pins are set for, the DONE LED is always turned on when i power on the board. I cannot connect to the board via JTAG...
5
5
 
simple example with timing problems
Hi, I wrote a simple stop watch for the Spartan 3 StarterKit. Unfortunately it seems to be unstable, i.e. sometimes when I release the button, the counter doesn't stop as it should. During synthesis I...
3
3
 
Need help on UNISIM.Vcomponents.all
Hi, I'm trying to port some code from Xilinx to Altera and I'm in a bit of a problem by not having UNISIM lib on Altera. I use only a few components from the unisim lib so may not be a big effort to...
4
4
 
high noise/signal in a simple serial to mono dac module
Hello I am working on playing simple 11 kbytes/second 8bit WAV data through my FPGA stereo jack. I used the following synthesis to play the sound data delivered through the serial interface. I also...
6
6
 
Virtex4 FX PPC and Fsl
Hi, I have the following problem: I have designed a peripheral with a Fsl bus. It works fine when I create and EDK Project with micoblaze. Now I wanted to switch to a Virtex 4 with a Power PC. I know...
1
1
 
ISE 9.2 and Windriver
Hi, my Windriver trial period has expired, and then I found out that the license costs $900 ?!? Is it possible to bypass windriver - e.g. by using the xilinx usb-cable ? I'm currently using the...
1
1
 
case statements- verilog to vhdl
I have the following scenario in verilog which i need to convert to vhdl always if reset . . . else case . . . end case // set default values case. . . . . end case end How do I convert this to vhdl....
7
7