Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Xilinx is cancelling the Virtex-E XCV1000E-FG860
Xilinx is canceling the Virtex-E XCV1000E-FG860. We are currently shipping a product that uses 13 of these chips on 4 different boards. Does anyone have any ideas on how to deal with this? One...
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Need a few Xilinx Spartan FPGAs
Hello, Does anyone have a few XCS30 -3TQ144C FPGAs around, or know a distributor who will sell in small quantity? I need about a dozen to finish off the last boards using that chip. I've just about...
 
How to independently program the embedded PowerPC in a Virtex?
Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded PowerPC independently from booting the whole FPGA via the Xilinx Platform Flash....
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Altera Cyc II config problems
Subject board has two 2C devices and a 3C device in a serial config chain. The 2C device's MSEL pins are jumper configurable to AS (for "self-config") or PS ("Software Config") config mode. The other...
 
Newbie: Testbench question
Hello, I have a question about instantiating a module in a verilog testbench. Sometimes the instantiation may have lots of inputs and output that you may not want to appear in the ModelSim simulation,...
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Turning off the DLL to run DDR2 at very low frequency
Hi, There's been a few discussions about this the last couple years, but it seems nothing ended with firm conclusions. What I would like to do is to run DDR2 at 25MHz (DDR50). I understand that to do...
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opb_intc + PowerPC
Hello. I have a problem with use opb_intc in my projekt In mhs: # External Interrupts PORT IrqSecond_pin = IrqSecond, DIR = I, SIGIS = Interrupt, SENSITIVITY = LEVEL_HIGH PORT IrqPci_pin = IrqPci, DIR...
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not inferred RAM, on QII
Hi, On some pretty obvious piece of VHDL (below) QuartusII does not inferred any RAM !!!!!! (whatever "width" value is...) Any help how to convince QII to use RAM and not LEs ??? (all ram options are...
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DCM configuration in Virtex-4 FPGA
Hi all, I'm having a little problem to implement a DCM. It's the first time i need it (to be able to use DDR SDRAM). Before i'm going to think about a design for a memory controller, i first want to...
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Celoxica RC1000
Hi All i am new to FPGA's and have picked up a celoxica rc1000pp (virtex 2000e) cheap, the downside...no manuals or software. i expected that (being an old bit of kit) the drivers and manuals would be...
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OPB_MDM functionality
hi, this is my question: Is opb_mdm used to load C code (from executable.elf) from SDRAM?. I have downloaded an aplication (executable.elf) to the Sdram. Due to the fault of a RS232 peripheral, I use...
 
XmdStub fails when connecting via JTAG.
Hi, I would like to know if anyone has received this message when he tries to start XMD. This message appears some times and I have to close Xmd Windows and start again so the message doesn't appear....
 
ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
Maia is a new tool which automatically creates HDL(*) testbenches from a vector-style description. The trivial test case below, for example, is a complete testbench for a 4-bit up-counter with reset....
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Problem writing quadrature decoder
Hi there - I am continuing to attempt to learn VHDL this weekend! Currently I'm trying to interface to the quadrature encoder on my Spartan 3E Starter Kit. It outputs normal quadrature signals. So, I...
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synchronous reset problems on FPGA
Hi, I am wondering if anyone of you have experienced this before. Here goes the reset problem I am facing now. asynchronous reset in FPGAs are usually a big NO-NO. from the articles I am reading, the...
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