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- Date
- Subject
- Replies
- 09-05-2005
- Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3...
- 2
- -
- 09-05-2005
- Area Estimation Issues
- 0
- 09-05-2005
- PPC405 32 bit aligned accesses
- 15
- 09-05-2005
- False values in Quartus In-System Memory Editor
- 6
- -
- 09-05-2005
- Nand Flash Emulator
- 0
- 09-05-2005
- Fastest input IOB on a Spartan-3?
- 8
- 09-05-2005
- Defining Environment variables inside EDK
- 2
- 09-05-2005
- Reprogramming one MAXII EPM1270 vs security bit set
- 2
- 09-05-2005
- Reading internal signals through a testbench.
- 4
- 09-05-2005
- coe file of Xilinx MAC FIR core??
- 1
- 09-05-2005
- Problem with interfacingT-VPACK with ALTERA QUIP5.0
- 4
- -
- 09-05-2005
- Quartus web edition simulation with off-chip logic?
- 0
- 09-04-2005
- Partial Reconfiguration : New Forum
- 1
- 09-04-2005
- Logic??
- 5
- -
- 09-04-2005
- IC design contract
- 0
- 09-03-2005
- Long Multiplication
- 2
- 09-03-2005
- High baud rate chips for RS232 protocol
- 6
- 09-03-2005
- Modelling latches in Verilog
- 2
- 09-03-2005
- The best way to sum 8 datas?
- 2
- 09-02-2005
- Platform Cable USB
- 2
- 09-02-2005
- Spartan 3 Ram Instantiation
- 8
- 09-02-2005
- gal16v8 CUPL problems
- 1
- 09-02-2005
- Creating higher bit multipliers from low bit.
- 2
- 09-02-2005
- XUP Virtex-II Pro "invalid target architecture"
- 9
- -
- 09-02-2005
- Modelsim simulation question
- 0
- 09-02-2005
- Multidimensional port.
- 3
- 09-02-2005
- OT: CPLD - SimuCAD S/W CD
- 5
- 09-02-2005
- I2C "SCL" line problem
- 6
- 09-01-2005
- Xilinx and Lattice tools on one machine?
- 2
- 09-01-2005
- Modelsim XE and multi-file Verilog projects
- 4
- -
- 09-01-2005
- FIFO PhysDesignRules:993
- 0
- 09-01-2005
- current!
- 3
- -
- 09-01-2005
- MicroBlaze: PLX PCI 9056 IP
- 0
- 09-01-2005
- Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.
- 2
- 09-01-2005
- "Perform Timing-Driven Packing and Placement" error?
- 4
- -
- 09-01-2005
- New FPGA development board.
- 0
- 09-01-2005
- A strange behavior
- 2
- 09-01-2005
- bare die (non packaged) FPGA, CPLD, controllers ?
- 4
- 09-01-2005
- CPLD CoolRunner-II - IO current limited to 8mA?
- 4
- 09-01-2005
- Mentor FPGA Advantage, a simple question
- 2
- 09-01-2005
- FS: Lot of 60 XCV1000 FPGAs
- 4
- -
- 08-31-2005
- New PCI Express Group
- 0
- 08-31-2005
- Spartan 3 Serdes
- 7
- 08-31-2005
- Spartan-3 LVDS driving TFT LCD panel..?
- 6
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