Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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noob question
Hi, when i synthesize this : architecture Behavioral of vga_test is constant MXINIT : integer := 100; constant MYINIT : integer := 100; signal mousex_reg,mousey_reg : unsigned(9 downto 0); signal...
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15 years ago
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delta sigma adc.....
hi....I want to implement Sigma Delta ADC in Spartan 3E starter kit....i have implemented it as xilinx's xapp-155.....in ise it works well for 8 bit....but give problem for 16 bit.....When i open it...
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15 years ago
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ATF750 for Proteus
Hi! I'm looking for the Atmel ATF750C library for Proteus but I'm unable to find it on both Atmel & Labcenter sites. Does anyone know where can I find this ? Or perhaps, any other application that can...
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15 years ago
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ANNC: Digital Power Management Webcast
Lattice is holding a webcast today Thursday, April 24th, "Digital Power Management for Analog Supplies." The presenter will be Shyam Chandra, from our mixed signal marketing group. If you're...
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15 years ago
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ACTEL FPGA static timing analysis
I am using actel 1280 FPGA. How to use the Timer to detect set up violations arising due to clock skew between two registers of a counter?
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15 years ago
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HydraXC + EDK
HI, I'm struggling with an EDK project and a HydraXC here. First of all I can't get the Hydra to work. I loaded a sample design (PPC linux) from the CD onto the SD card, inserted it and turned on the...
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15 years ago
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video stream transfer via UART and Bluetooth in FPGA
I need to send video stream over a bluetoth link , case 1 ) the video lise is some format (suggest a easy format) in CF compact flash card , I need to read this file and send it through UART, Kindly...
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15 years ago
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will there be any problem with diffrent version of sysgen & EDK
hi, I have ISE 9.1 + EDK 9.1 (all updates) Now i have downloaded the xilinx sysgen 10.1 (60 day trial) as 9.1 is not available also I have matlab R2006b will threre be any problem with versions , in...
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15 years ago
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superscalar processor design
Hi I am just wondering if somebody has some good sources for a superscalar processor implementation in VHDL? I have found a lot simple Implementations but struggle to find a superscalar one....
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15 years ago
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FPGA comeback
Hi I want to get into FPGA design after long time I was out of it. I did some work with ALTERRA long ago . I mainly did VHDL models for asic . I want to buy some FPGA board and to do some projects on...
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15 years ago
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Verilog state machines, latches, syntax and a bet!
Hi, A colleague and I are having a friendly debate on coding state machines in Verilog, targeting synthesis for FPGAs. Comments are very appreciated. I am NOT trying to start a holy war here regarding...
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15 years ago
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10.1 EDK - How can I create a user library in SDK?
Dear experts, I may need to build a few user libraries for PPC and MBZ targets, the libraries would be hardware independent, just computational modules. I've read this link the solution means that I...
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15 years ago
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the order in which some switches are turned on
Hi all, I have an array of N switches . Initially all are OFF. Somebody turns them ON in some order. It is possible that more switches are turned ON in the same moment. I need a device which shows me...
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16 years ago
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Can somebody help about Period Timing Constraints
Hi all, I don't understand is there any the relationship between the value of period constraints and my input clock? For my system, Board input clock is 50MHz, system works at 500MHz. When there is no...
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16 years ago
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FPGA Verilog state machine lock up
Hello, I am using Verilog to program a Xilinx FPGA. The program is basically a state machine with at least 32 states. There is an internal counter that counts and allows the state machine to move from...
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16 years ago
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