Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Virtex4 DCM doesn't work unless freezing cold
Hi everyone, We've been shipping a Virtex4 FX20 based product for a few months now with relatively few problems. However, we're seeing a 60+% failure rate in our latest batch of boards, characterized...
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15 years ago
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what's the difference between .rba & .rbb files ?
Hi , Bitgen generates as readback files ( .rba & .rbb) , but wich one contains exactly the data that is configured in the FPGA ? no one ? M.B
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15 years ago
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XUPV2P and EDK 10.1
Hi all, I'm glad to see that the XUPV2P board is now supported by EDK 10.1. However, setting the MPCM memory controller to work seems complex and up to now I hadn't success (256 MB DDR DIMM memory...
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15 years ago
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how to optimize this comparator for better synthesis result?
wire [6:0] length; wire [11:0] addr; assign len_lte=((addr[11:2]+length)
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15 years ago
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I use a ftp tool test my V5-based PCIE ethernet NIC controller.
1>uni-upload or uni-download,it works well.occasionally ,the NMI error is trigered if the PH credit is changed from (4)finite to (0)infinite . why can the PH credit become infinite? it is normal? 2>if...
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15 years ago
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XCF02S not seen in the JTAG chain
Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now. But like normal days I need to solve this issue asap and thought to ask the...
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15 years ago
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Hand-editing xilinx.sys
I have a systemACE based dev. platform for Virtex-5 and copy my ace files by hand from my linux system to my CF card. Everything works fine with the auto-generated file and the ace file. It also works...
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15 years ago
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PPC + APU + FSL + Xilkernel Problem
Hello, I currently working on a project in EDK 9.1. I have a PPC system with a custom peripheral the is connected to the PPC through FSL->FCB->APU. If I create an EDK project using microblaze and...
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15 years ago
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Style for Highly-Pipelined State Machines
I'm designing another FSM and I've run into the problem I always have when trying to pipeline them for high-speed designs. I'll show a simple example. STATE2: begin if (condition) begin state
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15 years ago
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Functional Simulation of Virtex-4 Block Memory
I am doing my first FPGA design. The design uses VHDL source with a few Xilinx cores (a Virtex-4 device will be used). One of the cores is block memory used as ROM. The design does not use an embedded...
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15 years ago
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floating point and logarithm in vhdl+xilinx
Please sombody help me. I am trying to write a vhdl code and i need to use floating point arithmetic and logarithm. I have downloaded ieee 2006 library but they do not synthesize in xilinx ISE. I have...
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15 years ago
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Chirp generator / CORDIC algo ?
Hello, I am on a project of developping a chirp generator on a FPGA. Reading from the internet I learned that the CORDIC algorithm is broadly used when we want to synthesis sin functions. My...
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15 years ago
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Virtex4 PPC405 - FPU problem
[first posted on ML403 - Virtex4 XC4VFX12 - PPC405 - Xilinx EDK V10.1 Hi, I have a working PPC405 design to which I want to add the APU FPU IP (enough acronyms?). I have used the wizard to configure...
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15 years ago
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parallel port using XSA-50
Hello All, I am in need of a tutorial for parallel port programming on the XSA-50 board. Can anyone suggest a great tutorial or program which will teach me how to send data from my XSA-50 board to the...
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15 years ago
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Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4)
Hello everybody, I'm a PhD student and I work on Partial Reconfiguration. I try to do the tutorial provided by Xilinx which is : "PR Flow Design Examples Using ISE 9.1.2 with PR10 Overlay Targeting...
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15 years ago
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